LS5909 Datasheet PDF - Micross

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LS5909
Micross

Part Number LS5909
Description Low Leakage
Page 1 Pages


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LS5909
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
The LS5909 is a high-performance monolithic dual
JFET featuring tight matching and low drift over
temperature specifications, and is targeted for use in a
wide range of precision instrumentation applications
where tight tracking is required.
FEATURES 
LOW DRIFT 
ULTRA LOW LEAKAGE 
LOW PINCHOFF 
ABSOLUTE MAXIMUM RATINGS  
| VGS12 / T| = 5µV/°C TYP. 
IG = 150fA TYP. 
Vp = 2V TYP. 
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
@ 25°C (unless otherwise noted) 
Maximum Temperatures 
improper orientation.
Storage Temperature 
65°C to +150°C 
(See Packaging Information).
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor  Note 1 
VGSS 
Gate Voltage to Drain or Source 
40V 
VDSO 
Drain to Source Voltage 
40V 
IG(f)  Gate Forward Current 
10mA 
LS5909 Benefits:
IG  Gate Reverse Current 
Maximum Power Dissipation 
10µA 
ƒ Tight Tracking
ƒ Good matching
ƒ Ultra Low Leakage
ƒ Low Drift
Device Dissipation @ Free Air  Total                 40mW @ +125°C 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL 
CHARACTERISTICS  VALUE  UNITS  CONDITIONS 
| VGS12 / T| max. 
DRIFT VS. 
TEMPERATURE 
40  µV/°C  VDG=10V, ID=30µA 
TA=55°C to +125°C 
| V GS12 | max. 
OFFSET VOLTAGE  15 
mV  VDG=10V, ID=30µA 
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
CHARACTERISTICS 
MIN. 
TYP.  MAX. 
UNITS 
CONDITIONS 
BVGSS 
BVGGO 
 
Breakdown Voltage 
GateToGate Breakdown 
TRANSCONDUCTANCE 
40 
40 
 
60  ‐‐ 
‐‐  ‐‐ 
  
V  VDS = 0                  ID=1nA 
V        IG= 1nA               ID= 0               IS= 0 
  
YfSS  Full Conduction  70 
YfS 
|YFS12 / Y FS| 
 
IDSS 
Click|IDSS12 / IDSS| 
Typical Operation 
Mismatch 
DRAIN CURRENT 
Full Conduction 
Mismatch at Full Conduction 
50 
‐‐ 
 
60 
‐‐ 
 
GATE VOLTAGE 
 
300  500 
µmho 
VDG= 10V         VGS= 0V      f = 1kHz 
To Buy100  200 
1  5 
  
400  1000 
2  5 
µmho 
% 
 
µA 
% 
     VDG= 10V         ID= 30µA      f = 1kHz 
 
 
VDG= 10V              VGS= 0V 
 
  
 
 
VGS(off) or Vp 
Pinchoff voltage 
0.6  2  4.5 
V 
VDS= 10V               ID= 1nA 
VGS(on) 
Operating Range 
‐‐  ‐‐  4 
V                VDS=10V                 ID=30µA 
 
GATE CURRENT 
    
 
 
IGmax. 
Operating 
‐‐  ‐‐  1 
pA 
VDG= 10V ID= 30µA 
IGmax. 
IGSSmax. 
IGSSmax. 
IGGO 
 
High Temperature 
At Full Conduction 
High Temperature 
GatetoGate Leakage 
OUTPUT CONDUCTANCE 
‐‐ 
‐‐ 
‐‐ 
‐‐ 
 
‐‐  1 
‐‐  2 
‐‐  5 
1  ‐‐ 
  
nA  TA= +125°C
 
pA  VDS =0V      VGS= 20V 
nA  TA= +125°C 
 
pA  VGG= 20V 
  
YOSS 
YOS 
|YOS12| 
Full Conduction 
Operating 
Differential 
‐‐  ‐‐  5 
 
‐‐  0.1  0.1 
µmho 
‐‐ 
0.01 
0.1   
VDG= 10V              VGS= 0V 
VDG=  10V            ID=30µA 
 
COMMON MODE REJECTION 
 
  
 
 
CMR 
CMR 
 
NF 
20 log |VGS12/VDS| 
20 log |VGS12/VDS| 
NOISE 
Figure 
‐‐  90  ‐‐ 
‐‐  90  ‐‐ 
    
‐‐  ‐‐  1 
dB  ∆VDS = 10 to 20V        ID=30µA 
  VDS = 5 to 10V         ID=30µA 
  VDS= 10V      VGS= 0V       RG= 10MΩ 
dB  f= 100Hz           NBW= 6Hz 
en 
Voltage 
‐‐ 
20  70 
nV/Hz 
VDG=10V   ID=30µA   f=10Hz  NBW=1Hz 
 
CAPACITANCE 
    
 
 
CISS  Input  ‐‐  ‐‐  3    VDS= 10V       VGS= 0V       f= 1MHz 
CRSS 
Reverse Transfer 
‐‐  ‐‐  1.5 
pF 
CDD 
DraintoDrain 
‐‐  ‐‐  0.1 
 
VDG = 20V    ID=30µA      
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
SOIC / PDIP (Top View)
Micross Components Europe
Available Packages:
LS5909 in PDIP / SOIC
LS5909 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.



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