32-bit ARM Cortex-M4/M0 microcontroller
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 Processor core
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
Running at frequencies of up to 204 MHz.
JTAG, Serial Wire Debug, and built-in NVIC.
Up to 264 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64 kB ROM containing boot code and on-chip software drivers.
128 bit general-purpose One-Time Programmable (OTP) memory.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
Two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
One SPI controller.
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
One standard I2C-bus interface with monitor mode and with standard I/O pins.
Two I2S interfaces, each with DMA support and with one input and one output.
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 January 2012
© NXP B.V. 2012. All rights reserved.
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