LMS7002M Datasheet PDF - Lime Microsystems

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LMS7002M
Lime Microsystems

Part Number LMS7002M
Description FPRF MIMO Transceiver IC
Page 27 Pages


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LMS7002M
FPRF MIMO Transceiver IC
With Integrated Microcontroller
SUMMARY FEATURES
Field Programmable Radio Frequency (FPRF) chip
Dual transceiver ideal for MIMO
User programmable on the fly
Continuous coverage of the 100 kHz - 3.8 GHz RF frequency
range
Digital interface to baseband with on chip integrated 12 bit
D/A and A/D converters
Programmable RF modulation bandwidth up to
160 MHz using analog interface
Programmable RF modulation bandwidth up to
60 MHz using digital interface
Supports both TDD and full duplex FDD
LimeLightdigital IQ interface JEDEC JESD207 TDD and
FDD compliant
Transceiver Signal Processor block employs advanced
techniques for enhanced performance
Single chip supports 2x2 MIMO. Multiple chips can be used
to implement higher order MIMO
On-chip RF calibration circuitry
Fully differential baseband signals, analog IQ
Few external components
Low voltage operation, 1.25, 1.4 and 1.8V. Integrated LDOs
to run on a single 1.8V supply voltage
On chip integrated microcontroller for simplified calibration,
tuning and control
Integrated clock PLL for flexible clock generation and
distribution
User definable analog and digital filters for customised
filtering
RF and base band Received Signal Strength Indicator (RSSI)
261 pin aQFN 11.5x11.5 mm package
Power down option
Serial port interface
Low power consumption, typical 880mW in full 2x2 MIMO
mode (550mW in SISO mode) using external LDOs
Multiple bypass modes for greater flexibility
APPLICATIONS
Broad band wireless communications
GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE
IEEE® xxx.xxx radios
WiFi operating in the Whitespace frequencies
Software Defined Radio (SDR)
Cognitive Radio
Unmanned Aerial Vehicle (UAV)
Other Whitespace applications
Document version: 2.8.0
RXINL
RXLNAL
RXLNAH
RXINH
RXLNAW
RXINW
RF
RSSI
RXLNAL
RXINL
RXLNAH
RXINH
RXLNAW
RXINW
RXMIX
RXTIA
RXLPF
RXPGA
ADC
ADC
RX LO
Chain
RX
Synthesizer
TX BB
LPF
TX BB
LPF
RXOUTI, RXOUTQ
RXOUTI, RXOUTQ
RXOUTSW
RXOUTSW
RXMIX
RXTIA
RXLPF
RXPGA
ADC
ADC
TXOUT1
TXOUT2
TXOUT1
TXOUT2
RF
RSSI
Switch
Connects to LNA
output in RF Loop Back
mode
Power
Det.
Power
Det.
TXPAD
RX BB
TXPAD
Switch
Switch
Connects to LNA
output in RF Loop Back
mode
Connects to LNA
output in RF Loop Back
mode
Power
Det.
Power
Det.
TXPAD
RX BB
TXPAD
Switch
Connects to LNA
output in RF Loop Back
mode
SPI
Micro
Controller
Clock PLL
TX BB
LPF
TXINI, TXINQ
TXMIX
TXLPF
DAC
DAC
TX LO
Chain
TX
Synthesizer
TXMIX
TXLPF
DAC
DAC
TX BB
LPF
TXINI, TXINQ
Figure 1: Functional block diagram
DLB



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LMS7002M FPRF MIMO Transceiver IC
GENERAL DESCRIPTION
LMS7002M is a fully integrated, multi-band, multi-standard RF
transceiver that is highly programmable. It combines Low Noise
Amplifiers (RXLNA), TX Power Amplifier Drivers (TXPAD)
receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesizers, RX
gain control, TX power control, the analog-to-digital and digital-to-
analog convertors (ADC/DACs) and has been designed to require very
few external components.
The top level architecture of LMS7002M transceiver is shown in Figure
1. The chip contains two transmit and two receive chains for achieving a
Multiple In Multiple Out (MIMO) platform. Both transmitters share one
PLL and both receivers share another. Transmit and receive chains are
all implemented as zero Intermediate Frequency (zero IF or ZIF)
architectures providing up to 160MHz RF modulation bandwidths
(equivalent to 80MHz baseband IQ bandwidth). For the purpose of
simplifying this document, the explanation for the functionality and
performance of the chip is based on one transmit and one receive
circuitry, given that the other two work in exact the same manner.
On the transmit side, In-phase and Quadrature IQ DAC data samples,
from the base band processor, are provided to the LMS7002M via the
LimeLightdigital IQ interface. LimeLightimplements the JESD207
standard IQ interface protocol as well as de facto IQ multiplexed
standard. JESD207 is Double Data Rate (DDR) by definition. In IQ
multiplexed mode LimeLightalso supports Single Data Rate (SDR).
The IQ samples are then pre-processed by the digital Transceiver
Signal Processor (TSP) for minimum analog / RF distortion and applied
to the on chip transmit DACs. The DACs generate analog IQ signals
which are provided for further processing to the analog/RF section.
Transmit low pass filters (TXLPF) remove the images generated by
zero hold effect of the DACs, as well as the DAC out-of-band noise. The
analog IQ signals are then mixed with the transmit PLL (TXPLL) output
to produce a modulated RF signal. This RF signal is then amplified by
one of two separate / selectable power amplifier drivers and two open-
drain differential outputs are provided as RF output for each MIMO
path.
The LMS7002M provides an RF loop back option which enables the TX
RF signal to be fed back into the baseband for calibration and test
purposes. The RF loop back signal is amplified by the loopback
amplifier in order to increase the dynamic range of the loop.
There are two additional loop back options implemented, one is an
analog base band (BB) loop back and another is a digital loop back
(DLB) as shown in Figure 1. The analog loop back is intended for
testing while the DLB can be used to verify the LMS7002M connectivity
to base band, FPGA, DSP or any other digital circuitry.
On the receive side, three separate inputs are provided each with a
dedicated LNA optimised for narrow or wide band operation. Each port
RF signal is first amplified by a programmable low noise amplifier
(RXLNA). The RF signal is then mixed with the receive PLL (RXPLL)
output to directly down convert to baseband. AGC steps can be
implemented by a BB trans-impedance amplifier (RXTIA) prior to the
programmable bandwidth low pass channel select / anti alias filters
(RXLPF). The received IQ signal is further amplified by a programmable
gain amplifier RXPGA. DC offset is applied at the input of RXTIA to
prevent saturation and to preserve the receive ADC‟s dynamic range.
The resulting analog receive IQ signals are converted into the digital
domain with on-chip receive ADCs. Following the ADCs, the signal
conditioning is performed by the digital Transceiver Signal Processor
(TSP) and the resulting signals are then provided to the BB via the
LimeLightdigital IQ interface.
The analog receive signals can also be provided off chip at RXOUTI
and RXOUTQ pins by closing the RXOUT switch. In this case it is
possible to power down the on chip ADCs/TSP and use external parts
which can be very useful for more resource demanding applications or
where higher signal resolution is required. A similar option is also
available on the TX side where the analog signal can be processed by
external components. The on chip DACs/TSP can be powered down
and analog inputs can be provided at TXINI and TXINQ pins.
Parameter
Operating Temperature Range
Storage Temperature Range
Operating Frequency Range
RF Modulation Bandwidth
Frequency Resolution
Analog Supply Voltage, High (VDDAH)
Analog Supply Voltage, Medium
(VDDAM)
Analog Supply Voltage, Low (VDDAL)
Digital Core Supply Voltage
Digital Peripheral (IO) Supply Voltage
TX Supply Current
RX Supply Current
Maximum RF Output Power
PLL Reference Clock
Interpolation/Decimation digital filters
stop band suppression
Min.
-40
-65
30
0.1
1.71
1.33
1.2
1.1
1.7
10
Typ.
25
25
1.8
1.4
1.25
1.2
2.5
350
420
0
Max.
85
125
3800
3800
60
160
24.8
1.89
1.47
1.3
1.3
3.6
52
108
Unit
°C
°C
MHz
MHz
Hz
V
V
V
V
V
mA
mA
dBm
MHz
dB
Condition/Comment
Extended by TSP NCOs
Through digital interface
Through analog interface
Using 52 MHz PLL reference clock
Used for TXPAD
Generated using integrated low-dropout regulators
(LDOs)
Generated using integrated LDOs
Generated using integrated LDOs
At -7 dBm output power, 2x2 MIMO, including the DACs
and TSP
For 2x2 MIMO, including the ADCs and TSP
Continuous Wave
Table 1: General specifications
LMS7002M
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LMS7002M FPRF MIMO Transceiver IC
Parameter
RF channel frequency range
Transmit Analog Input Impedance
Transmit Load Impedance at the Output
Pins
Transmit Differential I and Q Input
Current
Transmit Gain Control Range
Transmit Gain Control Step
TX Local Oscillator (LO) Leakage
RXLNAL Frequency Range
RXLNAH Frequency Range
RXLNAW Frequency Range
Min.
30
0.1
0.1
0.1
0.1
Noise Figure
2rd Order Input Intercept Point
3rd Order Input Intercept Point
Receive Gain Control Range
Receive Gain Control Step
0.5
Typ.
400
40
Max.
3800
3800
Unit
MHz
Ohms
Ohms
Condition/Comment
Extended by TSP NCOs
Differential, programmable
Differential, for maximum OIP3
625
uA
Differential
Common mode
70 dB TXTSP and TXPAD combined
1 dB
-60 dBc Calibrated
2000
MHz
Narrow band tunable, set by external matching circuit
3800
MHz
Narrow band tunable, set by external matching circuit
3800
MHz
Broad band tunable, set by external matching circuit
2.0 at 0.95GHz
2.5 dB at 2GHz
3.5 at 3.8GHz
50
dBm
Total receiver gain ~50 dB or more, Noise Figure
<3.5 dB in all bands. Two tone signals out of band.
4
dBm
Total receiver gain ~50 dB or more, Noise Figure
<3.5 dB in all bands. Two tone signals out of band.
70 dB RXLNA, RXTIA, RXPGA and RXTSP combined
1 1.5 dB
Table 2: General RF specifications
Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs
(RXINL, RXINH, RXINW) are provided to facilitate multi-band multi-
standard operation.
The functionality of the LMS7002M is fully controlled by a set of internal
registers which can be accessed through a serial port and rapidly
reprogrammed on the fly for advanced system architectures.
In order to enable full duplex operation, LMS7002M contains two
separate synthesisers (TXPLL, RXPLL) both usually driven from the
same reference clock source PLLCLK.
TX GAIN CONTROL
The LMS7002M transmitter has two programmable gain stages, where
the TSP provides digital gain control and the TXPAD gives
programmable gain of the RF signal.
TXINI
TXINQ
TXMIX
TXPAD
TXOUT1
TXOUT2
TXPLL
Figure 2: TX analog/RF gain control architecture
Parameter
Digital TSP Gain Control Range
TXPAD Gain Control Range
TXPAD Gain Step Size
TXPAD Gain Step Size
Min.
Typ.
15
55
1
2
Max.
Table 3: TX gain control
Unit
dB
dB
dB
dB
Condition/Comment
In steps of 1 LSB digital gain control
for the higher 10 steps
for the lower 20 steps
LMS7002M
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LMS7002M FPRF MIMO Transceiver IC
RX GAIN CONTROL
The LMS7002M receiver has three gain control elements, RXLNA,
RXTIA, and RXPGA. If required, additional gain control can be
implemented by RXTSP in digital domain.
RXLNA gain control consists of 30 dB with 1 dB steps at high gain
settings and 3 dB steps at low gain settings for AGC when large
adjacent channel blockers are present and a reduction in system noise
figure (NF) is acceptable.
RXTIA offers 3 dB of control range. RXTIA is intended for AGC steps
needed to reduce system gain prior to the channel filters when large in
band blockers are present. This gain can be under the control of the
baseband or fixed on calibration.
RXPGA provides gain control for the AGC if a constant RX signal level
at the ADC input is required. It has a 32 dB gain range control in 1 dB
steps.
RXINL
RXLNAL
RXINH
RXLNAH
RXLNAW
RXINW
RXMIX
RXTIA
RXLPF RXPGA
RXPLL
Figure 3: RX gain control architecture
RXOUTI
RXOUTQ
Parameter
Digital TSP Gain Control Range
RXLNA Gain Control Range
RXTIA Gain Control Range
RXPGA Gain Control Range
RXPGA Gain Step Size
Min.
Typ.
15
30
3
32
1
Max.
Table 4: RX gain control
SYNTHESISERS
The LMS7002M has two low phase noise synthesizers to enable full
duplex operation and both are capable of output frequencies up to
3.8 GHz. Each synthesizer uses fractional-N PLL architecture as shown
in Figure 4. The same reference frequency can be used for both
synthesizers and is flexible between 10 to 52 MHz clock frequencies.
The synthesizers produce complex outputs with suitable levels to drive
IQ mixers in both the TX and the RX paths. The transmit PLL could also
be routed via switches to the receive PLL so as to offer phase coherent
operation in TDD mode.
PFD
The LMS7002M can accept clipped sine as well as CMOS level signals
for the PLL reference clock. Both DC and AC coupling are supported as
shown in Figure 5. Internal buffer self-biasing must be enabled for AC
coupling mode. The PLL reference clock input can also be low voltage
CMOS (<1.2V) which is implemented by lowering the clock buffer
supply.
VDD
Unit
dB
dB
dB
dB
dB
Condition/Comment
In steps of 1 LSB digital gain control
1 and 3 dB steps
CHP
/N
Loop
Filter
~
VCO
Output
Divider
NINT, NFRAC
Figure 4: PLL architecture
90º
VDD
External
Reference
CLKBUF
External
Reference
CLKBUF
LMS7002M
VSS
(a)
VSS
Figure 5: PLL reference clock input buffer, (a) DC coupled (b) AC coupled
(b)
4



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