LMS6002D Datasheet PDF - Lime Microsystems

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LMS6002D
Lime Microsystems

Part Number LMS6002D
Description Multi-band Multi-standard Transceiver
Page 15 Pages


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LMS6002D
Multi-band Multi-standard
Transceiver with Integrated
Dual DACs and ADCs
SUMMARY FEATURES
Single chip transceiver covering 0.3-3.8GHz
frequency range
Digital interface to baseband with integrated 12 bit
D/A and A/D converters
Fully differential baseband signals
Few external components
Programmable modulation bandwidth: 1.5, 1.75, 2.5,
2.75, 3, 3.84, 5, 5.5, 6, 7, 8.75, 10, 12, 14, 20 and 28MHz
Supports both TDD and FDD operation modes
Low voltage operation, 1.8V and 3.3V
120 pin DQFN package
Power down option
Serial port interface
APPLICATIONS
Femtocell and Picocell base stations
Repeaters
Broadband wireless communication devices for
WCDMA/HSPA, LTE, GSM, CDMA2000, IEEE® 802.16x
radios
12
TXD[11:0]
TX_IQ_SEL
TX_CLK
RX_CLK_OUT
RX_CLK
RX_IQ_SEL
RXD[11:0]
12
22
IQ DACs
12
IDAC
QDAC
12
/2
TX Power
Control
TX Gain
Control
TXLPF TXVGA1 DAC TXMIX
LO Leakage
TXVGA2
PA1
DAC
0o 90o
TXPLL
PA2
AUXPA
LMS6002D
2
TXOUT1
TXOUT2
2
/2
12
IADC
QADC
12 IQ ADCs RXVGA2 RXLPF
RXOUTSW
22
RXPLL
0o 90o
RXVGA1 RXMIX
RX Power
Control
RX Gain
Control
LNA1
LNA2
2
2
LNA3
RXLNA 2
RXIN1
RXIN2
RXIN3
SPI
Figure 1: Functional block diagram
GENERAL DESCRIPTION
The LMS6002D is a fully integrated, multi-band, multi-standard RF
transceiver for 3GPP (WCDMA/HSPA, LTE), 3GPP2 (CDMA2000) and
4G LTE applications, as well as for GSM pico BTS. It combines the
Document version: 1.1.0
Last modified: 03/12/2012
© Copyright Lime Microsystems
LNA, PA driver, RX/TX mixers, RX/TX filters, synthesizers, RX gain
control, and TX power control with very few external components.
The information contained in this document is subject to change
without prior notice. Lime Microsystems assumes no responsibility
for its use, nor for infringement of patents or other rights of third
parties. Lime Microsystems' standard terms and conditions apply at
all times.



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LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
The top level architecture of LMS6002D transceiver is shown in Figure
1. Both transmitter and receiver are implemented as zero IF
architectures providing up to 28MHz modulation bandwidth (equivalent
to 14MHz baseband IQ bandwidth).
On the transmit side, IQ DAC samples from the baseband processor
are provided to the LMS6002D on a 12 bit multiplexed parallel CMOS
input level bus. Analog IQ signals are generated by on chip transmit
DACs. These are fed to the TXINI and TXINQ inputs. Transmit low pass
filters (TXLPF) remove the images generated by zero hold effect of the
DACs. The IQ signals are then amplified (TXVGA1) and DC offset is
inserted in the IQ path by LO leakage DACs in order to cancel the LO
leakage. The IQ signals are then mixed with the transmit PLL (TXPLL)
output to produce a modulated RF signal. This RF signal is then split
and amplified by two separate variable gain amplifiers (TXVGA2) and
two off chip outputs are provided as RF output.
mixed with the receive PLL (RXPLL) output to directly down convert to
baseband. Large AGC steps can be implemented by an IF amplifier
(RXVGA1) prior to the programmable bandwidth lowpass channel
select filters (RXLPF). The received IQ signal is further amplified by a
programmable gain amplifier RXVGA2. DC offset is applied at the input
of RXVGA2 to prevent saturation and to preserve receive the ADC(s)
dynamic range. The resulting analog receive IQ signals are converted
into the digital domain using the on chip receive ADCs and provided as
an output to the baseband processor on a multiplexed 12 bit CMOS
output level parallel bus. The receive clock, RX_CLK, is provided off
chip at the RX_CLK_OUT pin and can be used to synchronise with the
baseband digital receive data sampling clock.
By closing the RXOUT switch and powering down RXVGA2, the
RXOUTI and RXOUTQ pins can be used as IQ ADCs inputs. In this
configuration the ADCs can be used to measure two external signals,
such as an off chip PA temperature sensor or peak detector.
Transmitter gain control range of 56dB is provided by IF (TXVGA1,
31dB range) and RF (TXVGA2, 25 dB range) variable gain amplifiers.
Both TXVGAs have 1dB gain step control.
The LMS6002D provides an RF loop back option (see Figure 1) which
enables the TX RF signal to be fed back into the baseband for
calibration and test purposes. The RF loop back signal is amplified by
an auxiliary PA (AUXPA) in order to increase the dynamic range of the
loop.
On the receive side, three separate inputs are provided each with a
dedicated LNA. Each port preconditioned RF signal is first amplified by
a programmable low noise amplifier (RXLNA). The RF signal is then
Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs
(RXIN1, RXIN2, RXIN3) are provided to facilitate multi-band operation.
The functionality of the LMS6002D is fully controlled by a set of internal
registers which can be accessed through a serial port.
In order to enable full duplex operation, the LMS6002D contains two
separate synthesizers (TXPLL, RXPLL) both driven from the same
reference clock source PLLCLK. The PLLCLK signal is provided at the
PLLCLKOUT output pin and can be used as the baseband clock.
Differential signalling is done in the receive and transmit analog paths
throughout the chip.
Parameter
TRX RF Frequency Range
Baseband Bandwidth
Frequency Resolution
TRX 3.3V Supply
TRX 1.8V Supply
TX Supply Current
RX Supply Current
Digital Core Supply Voltage
Digital Peripheral (IO)
Supply Voltage
Ambient Temperature
Storage Temperature
Maximum RF Output Power
Absolute Maximum RF Input
Power
PLL Reference Clock
PLL Phase Noise
Condition/Comment
Using 41MHz PLL reference clock
At maximum gain
At maximum gain
Can go below 3.3V nominal to
support LV CMOS signalling
Continuous wave
No damage
For continuous LO frequency
range
1MHz offset
Min
0.3
0.75
3.1
1.7
1.7
1.7
-40
-65
23
23
Table 1: General specifications
Typ
3.3
1.8
280
220
1.8
3.3
25
6
-125
Max
3.8
14
2.4
3.5
1.9
1.9
3.5
85
125
41
Unit
GHz
MHz
Hz
V
V
mA
mA
V
V
oC
oC
dBm
dBm
MHz
dBc/Hz
LMS6002D
2
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Parameter
TRX RF Bandwidth
Transmit Input Impedance
Transmit Load Impedance
Transmit Differential I and Q
Input Voltages
Transmit Gain Control Range
Transmit Gain Control Step
TX LO Leakage
RX LNA1 Frequency Range
RX LNA2 Frequency Range
RX LNA3 Frequency Range
RX LNA1 Input Impedance
RX LNA2 Input Impedance
RX LNA3 Input Impedance
Receive Load Impedance
Receive Load Capacitance
Noise Figure
3rd Order Input Referred
Intercept Point
Receive Gain Control Range
Receive Gain Control Step
Condition/Comment
Differential, programmable
Differential
Differential
Common mode
TXVGA1, TXVGA2
LO leakage not calibrated
Narrow band
Narrow band
Broad band
Differential
Differential
Differential
Differential
LNA1 at 0.95GHz
LNA2 at 1.95GHz
LNA3 at 1.95GHz
LNA2 at Mid. Gain
RXLNA, RXVGA1, RXVGA2
RXVGA1, not log-linear
RXVGA2
Min
0.3
0.3
1.5
0.3
Table 2: General RF specifications
Typ
100
65
250
65
56
1
-50
50
50
200
2k
5
3.5
5.5
10
-1
61
3
Max Unit
3.8 GHz
Ohms
Ohms
mVpp
mV
dB
dB
dBc
2.8 GHz
3.8 GHz
3.0 GHz
Ohms
Ohms
Ohms
Ohms
pF
dB
dBm
dB
1 dB
TX GAIN CONTROL
The LMS6002D transmitter has two programmable gain stages,
TXVGA1 is located in the IF section and TXVGA2 is in the RF section,
(see Figure 2). TXVGA1 is implemented on the I and Q branches but
controlled by a single control word. TXVGA2 consists of 2 amplifiers
one for each of the transmitter outputs, however only one of these
output amplifiers can be active at any time.
Note: The TXLPF has a gain of 6dB or 0dB when bypassed.
2 TXLPF TXVGA1 DAC
TXMIX
LO Leakage
TXVGA2
2
PA1
2
DAC
0o 90o
2
PA2
TXPLL
Figure 2: TX gain control architecture
Parameter
TXLPF Gain
TXVGA1 Gain Control Range
TXVGA1 Gain Step Size
TXVGA2 Gain Control Range
TXVGA2 Gain Step Size
Condition
0 dB gain when bypassed
Guaranteed monotonic
Guaranteed monotonic
Table 3: TX gain control
Min Typ
0
31
1
25
1
Max
6
Unit
dB
dB
dB
dB
dB
LMS6002D
3
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RX GAIN CONTROL
The LMS6002D receiver has three gain control elements, RXLNA,
RXVGA1, and RXVGA2 (see Figure 3). RXLNA gain control consists of
a single 6dB step for AGC when large in co-channel blockers are
present and a reduction in system NF is acceptable. The main LNAs
(LNA1 and LNA2) have fine gain control via a 6 bit word which offers
±6dB control intended for frequency correction when large input
bandwidths are required.
RXVGA1 offers 25dB of control range, a 7 bit control word is used and
the response is not log-linear. Maximum step size is 1dB. RXVGA1 is
intended for AGC steps needed to reduce system gain prior to the
channel filters when large in band blockers are present. This gain can
be under control of the baseband or fixed on calibration.
RXVGA2 provides the bulk of gain control for AGC if a constant RX
signal level at the ADC input is required. It has 30dB gain range control
in 3dB steps.
Note: RXLPF has a gain of 0dB when bypassed.
RXPLL
0o 90o
2
2
RXVGA2 RXLPF RXVGA1 RXMIX
LNA1
LNA2
2
2
LNA3
2
RXLNA
Figure 3: RX gain control architecture
Parameter
RXLNA Gain Control Range
RXVGA1 Gain Control Range
RXVGA1 Gain Step Size
RXLPF Gain
RXVGA2 Gain Control Range
RXVGA2 Gain Step Size
Condition
Single step
Not log-linear
0 dB gain when bypassed
Guaranteed monotonic
Min Typ Max Unit
0 6 dB
25 dB
1 dB
0 6 dB
30 dB
3 dB
Table 4: RX gain control
SYNTHESIZERS
LMS6002D has two low phase noise synthesizers to enable full duplex
operation. Both synthesizers are capable of output frequencies up to
3.8GHz. Each synthesizer uses a fractional-N PLL architecture as
shown in Figure 4. The same reference frequency is used for both
synthesisers and is flexible between 23 to 41MHz. The synthesizers
produce a complex output with suitable level to drive IQ mixers in both
the TX and the RX paths.
The LMS6002D can accept clipped sine as well as the CMOS level
signals as the PLL reference clock. Both DC and AC coupling are
supported as shown in Figure 5. Internal buffer self biasing must be
enabled for AC coupling mode. PLL reference clock input can also be
low voltage CMOS (2.5V or 1.8V, for example) which is implemented by
lowering clock buffer supply PVDDSPI33.
External
Loop
Filter
PFD CHP
/N
VCO
SD
NINT, NFRAC
Figure 4: PLL architecture
0o
90o
LMS6002D
4
© Copyright Lime Microsystems



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