LM3S8962 Datasheet PDF - Luminary Micro


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LM3S8962
Luminary Micro

Part Number LM3S8962
Description Microcontroller
Page 30 Pages

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PRELIMINARY
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LM3S8962 Microcontroller
DATA SHEET
DS-LM3S8962-1582
Copyright © 2007 Luminary Micro, Inc.



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Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and Luminary Micro and the Luminary Micro logo are
trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex
is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2 September 02, 2007
Preliminary



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LM3S8962 Microcontroller
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Table of Contents
About This Document .................................................................................................................... 21
Audience .............................................................................................................................................. 21
About This Manual ................................................................................................................................ 21
Related Documents ............................................................................................................................... 21
Documentation Conventions .................................................................................................................. 21
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 23
Product Features ...................................................................................................................... 23
Target Applications .................................................................................................................... 29
High-Level Block Diagram ......................................................................................................... 30
Functional Overview .................................................................................................................. 31
ARM Cortex™-M3 ..................................................................................................................... 31
Motor Control Peripherals .......................................................................................................... 31
Analog Peripherals .................................................................................................................... 32
Serial Communications Peripherals ............................................................................................ 33
System Peripherals ................................................................................................................... 35
Memory Peripherals .................................................................................................................. 35
Additional Features ................................................................................................................... 36
Hardware Details ...................................................................................................................... 37
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 38
Block Diagram .......................................................................................................................... 39
Functional Description ............................................................................................................... 39
Serial Wire and JTAG Debug ..................................................................................................... 39
Embedded Trace Macrocell (ETM) ............................................................................................. 40
Trace Port Interface Unit (TPIU) ................................................................................................. 40
ROM Table ............................................................................................................................... 40
Memory Protection Unit (MPU) ................................................................................................... 40
Nested Vectored Interrupt Controller (NVIC) ................................................................................ 40
3 Memory Map ....................................................................................................................... 44
4 Interrupts ............................................................................................................................ 46
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
JTAG Interface .................................................................................................................... 49
Block Diagram .......................................................................................................................... 50
Functional Description ............................................................................................................... 50
JTAG Interface Pins .................................................................................................................. 51
JTAG TAP Controller ................................................................................................................. 52
Shift Registers .......................................................................................................................... 53
Operational Considerations ........................................................................................................ 53
Initialization and Configuration ................................................................................................... 56
Register Descriptions ................................................................................................................ 56
Instruction Register (IR) ............................................................................................................. 56
Data Registers .......................................................................................................................... 58
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 60
Functional Description ............................................................................................................... 60
Device Identification .................................................................................................................. 60
Reset Control ............................................................................................................................ 60
September 02, 2007
Preliminary
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6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
Power Control ........................................................................................................................... 63
Clock Control ............................................................................................................................ 63
System Control ......................................................................................................................... 65
Initialization and Configuration ................................................................................................... 66
Register Map ............................................................................................................................ 66
Register Descriptions ................................................................................................................ 67
Hibernation Module .......................................................................................................... 121
Block Diagram ........................................................................................................................ 122
Functional Description ............................................................................................................. 122
Register Access Timing ........................................................................................................... 122
Clock Source .......................................................................................................................... 123
Battery Management ............................................................................................................... 123
Real-Time Clock ...................................................................................................................... 123
Non-Volatile Memory ............................................................................................................... 124
Power Control ......................................................................................................................... 124
Interrupts and Status ............................................................................................................... 124
Initialization and Configuration ................................................................................................. 125
Initialization ............................................................................................................................. 125
RTC Match Functionality (No Hibernation) ................................................................................ 125
RTC Match/Wake-Up from Hibernation ..................................................................................... 125
External Wake-Up from Hibernation .......................................................................................... 126
RTC/External Wake-Up from Hibernation .................................................................................. 126
Register Map .......................................................................................................................... 126
Register Descriptions .............................................................................................................. 127
Internal Memory ............................................................................................................... 140
Block Diagram ........................................................................................................................ 140
Functional Description ............................................................................................................. 140
SRAM Memory ........................................................................................................................ 140
Flash Memory ......................................................................................................................... 141
Flash Memory Initialization and Configuration ........................................................................... 142
Flash Programming ................................................................................................................. 142
Nonvolatile Register Programming ........................................................................................... 143
Register Map .......................................................................................................................... 143
Flash Register Descriptions (Flash Control Offset) ..................................................................... 144
Flash Register Descriptions (System Control Offset) .................................................................. 151
General-Purpose Input/Outputs (GPIOs) ....................................................................... 164
Functional Description ............................................................................................................. 164
Data Control ........................................................................................................................... 164
Interrupt Control ...................................................................................................................... 165
Mode Control .......................................................................................................................... 166
Commit Control ....................................................................................................................... 166
Pad Control ............................................................................................................................. 166
Identification ........................................................................................................................... 167
Initialization and Configuration ................................................................................................. 167
Register Map .......................................................................................................................... 168
Register Descriptions .............................................................................................................. 170
4 September 02, 2007
Preliminary




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