LM3668 Datasheet PDF - National Semiconductor


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LM3668
National Semiconductor

Part Number LM3668
Description High Efficiency Dual Mode Single Inductor Buck-Boost DC/DC Converter
Page 16 Pages

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June 2007
LM3668
1A, High Efficiency Dual Mode Single Inductor Buck-Boost
DC/DC Converter
General Description
The LM3668 is a synchornous buck or boost DC-DC convert-
er optimized for powering low voltage circuits from a Li-Ion
battery and input voltage rails between 2.5V and 5.5V. It has
the capability to support up to 1A output current over a output
voltage range of 2.8V/3.3V. The LM3668 regulates the output
voltage over the complete input voltage range by automati-
cally switching between buck or boost modes depending on
the input voltage.
The LM3668 has 2 N-channel MOSFETS and 2 P-channel
MOSFETS arranged in a topology that provides continuous
operation through the buck and boost operating modes.
There is a MODE pin that allows the user to choose between
an intelligent automatic PFM-PWM mode operation and
forced PWM operation. During PWM mode, a fixed-frequency
2.2MHz (typ.) is used. PWM mode drives load up to 1A. Hys-
teretic PFM mode extends the battery life through reduction
of the quiescent current to 45µA (typ.) at light loads during
system standby. Internal synchronous retification provides
high efficiency. In shutdown mode (Enable pin pulled low) the
device turns off and reduces battery consumption to 0.01µA
(typ.).
The LM3668 is available in a 12-pin LLP package. A high
switching frequency of 2.2MHz (typ.) allows the use of tiny
surface-mount components including a 2.2µH inductor, a
10µF input capacitor, and a 22µF output capacitor.
Features
45µA typical quiescent current
1A maximum load current for VIN = 2.8V to 5.5V
800mA maximum load current for VIN = 2.7V
600mA maximum load current for VIN = 2.5V
2.2 MHz PWM fixed switching frequency (typ.)
Automatic PFM-PWM Mode or Forced PWM Mode
Wide Input Voltage Range: 2.5V to 5.5V
Output Voltage Range: 2.8V/3.3V
Internal synchronous rectification for high efficiency
Internal soft start: 600µs Maximum start-up time
0.01µA typical shutdown current
Current overload and Thermal shutdown protection
Frequency Sync Pin: 1.6Mhz to 2.7MHz
Applications
Handset Peripherals
MP3 players
Pre-Regulation for linear regulators
PDAs
Portable Hard Disk Drives
WiMax Modems
Typical Applications
Typical Application Circuit
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20191425
Efficiency at 3.3V Output
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Functional Block Diagram
FIGURE 1. Functional Block Diagram
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Connection Diagrams and package
Mark Information
Top View
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Bottom View
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Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
VOUT
SW2
PGND
SW1
PVIN
EN
VDD
NC*
SGND
MODE/SYNC
VSEL
FB
Description
Connect to output capacitor.
Switching Node connection to the internal PFET switch (P2) and
NFET synchronous rectifier (N2).
Power Ground.
Switching Node connection to the internal PFET switch (P1) and
NFET synchronous rectifier (N1).
Supply to the power switch, connect to the input capacitor.
Enable Input. Set this digital input high for normal operation. For
shutdown, set low.
Signal Supply input. If board layout is not optimum an optional
1µF ceramic capacitor is suggested as close to this pin as
possible.
No connect. Connect this pin to GND on PCB layout.
Analog and Control Ground.
Mode = LOW, Automatic Mode. Mode= HI, Forced PWM Mode
SYNC = external clock synchronization from 1.6MHz to 2.7MHz
(When SYNC function is used, device is forced in PWM mode).
Logic input low = 2.8V and logic high = 3.3V to set output Voltage.
Feedback Analog Input. Connect to the output at the output filter.
Ordering Information
Order Number
LM3668SD - 3.3
LM3668SDX - 3.3
Package
LLP-12
NSC Package
Marking
S016B
S016B
Supplied As
1000 units, Tape and Reel
4500 units, Tape and Reel
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, VDD Pin: Voltage to SGND &
PGND
FB, EN,MODE,SYNC pin:
PGND to SGND
Continuous Power Dissipation
(Note 3)
Maximum Junction Temperature
(TJ-MAX)
−0.2V to +6.0V
(PGND &
SGND-0.2V)
(PGND &
SGND-0.2V) to
(PVIN + 0.2)
-0.2V to 0.2V
Internally Limited
+125°C
Storage Temperature Range
Maximum Lead Temperature
(Soldering, 10 sec)
−65°C to +150°C
+260°C
Operating Ratings
Input Voltage Range
Recommended Load Current
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(Note 3)
2.5V to 5.5V
0mA to 1A
−40°C to +125°C
−40°C to +85°C
Thermal Properties
Junction-to-Ambient Thermal Resistance (θJA),
Leadless Lead frame Package (Note 5)
34°C/W
Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for TJ = +25°C. Limits in boldface type
apply over the full operating junction temperature range (−40°C = TJ +85°C). Unless otherwise noted: specifications apply to
the LM3668. VIN = 3.6V = EN, VOUT = 3.3V, CIN = 10 µF & COUT = 22µF (Note 8).
Symbol
Parameter
Conditions
Min Typ Max Units
VFB
ILIM
ISHDN
IQ_PFM
Feedback Voltage
Switch Peak Current Limit
Shutdown Supply Current
DC Bias Current in PFM
(Note 7)
Open loop(Note 2)
EN =0V
No load, device is not switching
(FB Forced higher than
programmed output voltage)
-3
1.6
1.85
0.01
45
3
2.05
1
60
%
A
µA
µA
IQ_PWM
RDSON(P)
RDSON(N)
FOSC
FSYNC
VIH
DC Bias Current in PWM
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Internal Oscillator Frequency
Sync Frequency Range
Logic High Input for EN, MODE/
SYNC pins
PWM Mode, No Switching
Switches P1 and P2
Switches N1 and N2
PWM Mode
VIN = 3.6V
600 750
µA
130 180
m
100 150
m
1.9 2.2 2.5 MHz
1.6 2.7 MHz
1.1 V
VIL Logic Low Input for EN, MODES/
SYNC pins
0.4 V
IEN, MODE, SYNC EN,MODES/SYNC pin Input Current
0.3 1
µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limits is activated).
Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125ºC), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kresistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 5: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 101.6mm x 76.2mm x 1.6mm. Thickness of the copper layers are 2oz/1oz/1oz/
2oz. The middle layer of the board is 60mm x 60mm. Ambient temperature in simulation is 22°C, still air.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
Note 6: All voltage is with respect to SGND.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: CIN and COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
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