LE82GM965 Datasheet PDF - Intel

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LE82GM965
Intel

Part Number LE82GM965
Description Mobile Chipset
Page 30 Pages


LE82GM965 datasheet pdf
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Mobile Intel® 965 Express
Chipset Family
Datasheet
Revision 003
June 2007
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www.DataShIONeTFeHOtE4RRUMWA.IcTSoIEOm,NTOINATNHYISINDTOELCLUEMCETNUATLISPRPORPOEVRITDYEDRIIGNHCTSONISNEGCRTAINOTNEWD IBTYHTIHNITSELD®OCPURMOEDNUTC. TESX.CNEOPTLAICSEPNRSOEV, IEDXEPDREISNSINOTRELIM'SPTLEIERDM,SBAYNEDSTCOOPNPDEILTOIORNS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics
of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with
this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
This device is protected by U.S. patent numbers 5,315,448 and 6,516,132, and other intellectual property rights. The use of Macrovision's copy
protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless
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I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Intel® Active Management Technology requires the platform to have an Intel AMT-enabled chipset, network hardware and software, as well as
connection with a power source and a corporate network connection. With regard to notebooks, Intel AMT may not be available or certain capabilities
may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information,
see http://www.intel.com/technology/iamt.
Intel, Intel SpeedStep, Intel Core, Centrino, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
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Contents
1 Introduction ............................................................................................................ 11
1.1 Mobile Intel® PM965 Express Chipset Feature Support ........................................... 12
1.1.1 Processor Support .................................................................................. 12
1.1.2 System Memory Support ......................................................................... 12
1.1.3 Discrete Graphics using PCI Express* Graphics Attach Port .......................... 13
1.1.4 Direct Management Interface ................................................................... 13
1.1.5 Power Management ................................................................................ 13
1.1.6 Security and Manageability (Intel® Active Management Technology)............. 13
1.1.7 Package ................................................................................................ 14
1.1.8 Intel® Stable Image Platform Program ..................................................... 14
1.2 Mobile Intel® GM965 Express Chipset Feature Support .......................................... 14
1.2.1 PCI Express Graphics Attach Port.............................................................. 14
1.2.2 Integrated Graphics................................................................................ 14
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
Analog CRT .............................................................................. 15
Dual Channel LVDS ................................................................... 15
Analog TV-Out.......................................................................... 15
SDVO Ports .............................................................................. 16
1.2.3 Power Management ................................................................................ 16
1.2.4 Intel Stable Image Platform Program ........................................................ 16
1.3 Mobile Intel® GL960 Express Chipset Feature Support ........................................... 16
1.3.1 Processor Support .................................................................................. 16
1.3.2 System Memory Support ......................................................................... 17
1.3.3 PCI Express Graphics Attach Port.............................................................. 17
1.3.4 Integrated Graphics................................................................................ 17
1.3.5 ICH Support .......................................................................................... 17
1.3.6 Power Management ................................................................................ 17
1.3.7 Intel Advanced Management Technology ................................................... 17
1.3.8 Intel Stable Image Platform Program ........................................................ 17
1.4 Mobile Intel® GME965 Express Chipset Feature Support......................................... 17
1.4.1 Integrated Graphics................................................................................ 17
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1.4.1.1 Analog TV-Out.......................................................................... 17
1.5 Mobile Intel® GLE960 Express Chipset Feature Support ......................................... 18
1.5.1 Integrated Graphics................................................................................ 18
1.5.1.1 Analog TV-Out.......................................................................... 18
1.6 Terminology ..................................................................................................... 18
1.7 Reference Documents ........................................................................................ 19
2 Signal Description ................................................................................................... 21
2.1 Host Interface................................................................................................... 22
2.1.1 Host Interface Signals............................................................................. 22
2.2 DDR2 Memory Interface ..................................................................................... 25
2.2.1 DDR2 Memory Channel A Interface ........................................................... 25
2.2.2 DDR2 Memory Channel B Interface ........................................................... 26
2.2.3 DDR2 Memory Common Signals ............................................................... 27
2.2.4 DDR2 Memory Reference and Compensation .............................................. 28
2.3 PCI Express Based Graphics Interface Signals ....................................................... 28
2.3.1 Serial DVO and PCI Express*-Based Graphics Signal Mapping....................... 28
2.4 DMI – (G)MCH to ICH Serial Interface .................................................................. 29
2.5 Integrated Graphics Interface Signals .................................................................. 30
2.5.1 CRT DAC Signals .................................................................................... 30
2.5.2 Analog TV-out Signals............................................................................. 31
Datasheet
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2.6
2.7
2.8
2.9
2.10
2.5.3 LVDS Signals .........................................................................................32
2.5.4 Serial DVO Interface ...............................................................................33
2.5.5 Display Data Channel (DDC) and GMBUS Support .......................................34
Intel® Management Engine Interface Signals ........................................................35
PLL Signals .......................................................................................................35
Reset and Miscellaneous Signals ..........................................................................36
Non-Critical to Function (NCTF) ...........................................................................37
Power and Ground .............................................................................................37
3 Host Interface..........................................................................................................41
3.1 FSB Source Synchronous Transfers ......................................................................41
3.2 FSB IOQ Depth..................................................................................................41
3.3 FSB OOQ Depth.................................................................................................41
3.4 FSB AGTL+ Termination .....................................................................................41
3.5 FSB Dynamic Bus Inversion.................................................................................41
3.6 FSB Interrupt Overview ......................................................................................42
3.7 APIC Cluster Mode Support .................................................................................42
4 System Address Map ................................................................................................43
4.1 Legacy Address Range........................................................................................45
4.1.1 DOS Range (0000_0000h – 0009_FFFFh)...................................................47
4.1.2 Legacy Video Area (000A_0000h to 000B_FFFFh)........................................47
4.1.2.1 Compatible SMRAM Address Range (000A_0000h to 000B_FFFFh) ...47
4.1.2.2 Monochrome Adapter (MDA) Range (000B_0000h to 000B_7FFFh)...47
4.1.3 Expansion Area (000C_0000h to 000D_FFFFh) ...........................................47
4.1.4 Extended System BIOS Area (000E_0000h to 000E_FFFFh) ..........................48
4.1.5 System BIOS Area (000F_0000h to 000F_FFFFh) ........................................48
4.1.6 Programmable Attribute Map (PAM) Memory Area Details .............................49
4.2 Main Memory Address Range (1 MB to TOLUD) ......................................................49
4.2.1 ISA Hole (15 MB to 16 MB) ......................................................................50
4.2.2 Top Segment (TSEG) ..............................................................................51
4.2.3 Pre-allocated Memory..............................................................................51
4.3 PCI Memory Address Range (TOLUD to 4 GB) ........................................................52
4.3.1 APIC Configuration Space (FEC0_0000h to FECF_FFFFh) ..............................54
4.3.2 HSEG (FEDA_0000h to FEDB_FFFFh) .........................................................54
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4.3.3 FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF) .............................54
4.3.4 High BIOS Area ......................................................................................54
4.4 Main Memory Address Space (4 GB to TOUUD) ......................................................55
4.4.1 Memory Re-Map Background ....................................................................55
4.4.2 Memory Remapping (or Reclaiming) ..........................................................56
4.5 PCI Express Configuration Address Space..............................................................56
4.5.1 PCI Express Graphics Attach ....................................................................56
4.5.2 Graphics Aperture...................................................................................56
4.6 Graphics Memory Address Ranges........................................................................57
4.6.1 Graphics Register Ranges ........................................................................57
4.6.2 I/O Mapped Access to Device 2 MMIO Space ..............................................57
4.7 System Management Mode (SMM) .......................................................................59
4.7.1 SMM Space Definition ..............................................................................59
4.8 SMM Space Restrictions ......................................................................................60
4.8.1 SMM Space Combinations ........................................................................60
4.8.2 SMM Control Combinations.......................................................................60
4.8.3 SMM Space Decode and Transaction Handling.............................................61
4.8.4 Processor WB Transaction to an Enabled SMM Address Space .......................61
4.9 Memory Shadowing............................................................................................61
4.10 I/O Address Space .............................................................................................61
4.10.1 PCI Express I/O Address Mapping .............................................................62
4 Datasheet



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