LCMXO2-7000ZE Datasheet PDF - Lattice

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LCMXO2-7000ZE
Lattice

Part Number LCMXO2-7000ZE
Description MachXO2 Family
Page 30 Pages


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MachXO2™ Family Data Sheet
DS1035 Version 01.9, April 2012



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MachXO2 Family Data Sheet
Introduction
March 2012
Features
Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and
19 to 335 I/Os
Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
Embedded and Distributed Memory
• Up to 240 Kbits sysMEM™ Embedded Block
RAM
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
On-Chip User Flash Memory
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and
JTAG interfaces
• Can be used as soft processor PROM or as
Flash memory
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
DQS support
High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Data Sheet DS1035
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
interfaces (top and bottom sides only)
• Up to two analog PLLs per device with
fractional-n frequency synthesis
– Wide input frequency range (10 MHz to
400 MHz)
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2C
• Supports background programming of non-vola-
tile memory
• Optional dual boot with external SPI memory
TransFR™ Reconfiguration
• In-field logic update while system operates
Enhanced System Level Support
• On-chip hardened functions: SPI, I2C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Broad Range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
fpBGA, QFN package options
• Small footprint package options
– As small as 2.5x2.5mm
• Density migration supported
• Advanced halogen-free packaging
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1 DS1035 Introduction_01.5



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Introduction
MachXO2 Family Data Sheet
Table 1-1. MachXO2™ Family Selection Guide
LUTs
Distributed RAM (Kbits)
EBR SRAM (Kbits)
XO2-256
256
2
0
XO2-640
640
5
18
XO2-640U1
640
5
64
XO2-1200
1280
10
64
Number of EBR SRAM
Blocks (9 Kbits/block)
0
277
UFM (Kbits)
HC2
Device Options HE3
ZE4
Number of PLLs
Hardened Functions:
I2C
SPI
Timer/Counter
Packages
25 WLCSP5
(2.5 x 2.5mm, 0.4mm)
32 QFN6
(5 x 5mm, 0.5mm)
0
0
2
1
1
22
24 64 64
✓✓✓
01
22
11
11
1
2
1
1
19
64 ucBGA
(4 x 4mm, 0.4mm)
45
100 TQFP
(14 x 14mm)
56 79
80
132 csBGA
(8 x 8mm, 0.5mm)
56 80
105
144 TQFP
(20 x 20mm)
108 108
256 caBGA
(14 x 14mm, 0.8mm)
256 ftBGA
(17 x 17mm, 1.0mm)
332 caBGA
(17 x 17mm, 0.8mm)
484 fpBGA
(23 x 23mm, 1.0mm)
1. Ultra high I/O device.
2. High performance with regulator – VCC = 2.5V, 3.3V
3. High performance without regulator – VCC = 1.2V
4. Low power without regulator – VCC = 1.2V
5. WLCSP package only available for ZE devices.
6. QFN package only available for HC and ZE devices.
XO2-1200U1
1280
10
74
XO2-2000
2112
16
74
88
80 80
✓✓
11
2
1
1
I/Os
2
1
1
80
105
112
207
207 207
XO2-2000U1
2112
16
92
XO2-4000
4320
34
92
10 10
96 96
✓✓
✓✓
22
22
11
11
105
115
207
207
275
279 279
XO2-7000
6864
54
240
26
256
2
2
1
1
115
207
207
279
335
Introduction
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-
engineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These fea-
tures allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has sev-
eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
1-2



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Introduction
MachXO2 Family Data Sheet
and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)
devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-
ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC
devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE
and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage
all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same
package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range
of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.
The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-
bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-
down and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may
be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-
ilar state machines.
The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These
devices can also configure themselves from external SPI Flash or be configured by an external master through the
JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using
external Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of
reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft
core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-
ing their productivity.
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