LC863420C Datasheet PDF - Sanyo Semicon Device

Sanyo Semicon Device

Part Number LC863420C
Description (LC8634xxC) 8-Bit Single-Chip Microcontroller
Page 18 Pages

LC863420C datasheet pdf
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Ordering number : ENA0117A
48K/40K/32K/28K/24K/20K/16K-byte ROM,
on-chip 640/512-byte RAM and 352x9 bit OSD RAM
8-bit 1-chip Microcontroller
The LC863448C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip functional
CPU : Operable at a minimum bus cycle time of 0.424µs
On-chip ROM capacity
Program ROM : 48K/40K/32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
On-chip RAM capacity : 640/512 bytes
OSD RAM : 352×9 bits
Closed-Caption TV controller and the on-screen display controller
Closed-Caption data slicer
Four channels×6-bit AD Converter
Three channels×7-bit PWM
16-bit timer/counter, 14-bit base timer
IIC-bus compliant serial interface circuit (Multi-master type)
ROM correction function
• 12-source 8-vectored interrupt system
Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function
All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in
advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in
an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips.
IIC is a trademark of Philips Corporation.
62006HKIM No.A0117-1/18

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„Read-Only Memory (ROM) :
49152×8 bits / 40960×8 bits / 32768×8 bits /
28672×8 bits / 24576×8 bits / 20480×8 bits /
16384×8 bits for program
16128×8 bits for CGROM
„Random Access Memory (RAM) :
512×8 bits (working area) : LC863448C/40C
384×8 bits (working area) : LC863432C/28C/24C/20C/16C
128×8 bits (working or ROM correction function)
352×9 bits (for CRT display)
„OSD Functions
Screen display : 36 characters×16 lines (by software)
: 352 words (9 bits per word)
Display area : 36 words×8 lines
Control area : 8 words×8 lines
Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts (Ex. 16×16 dot character font×2)
At least 111 characters need to be divide between a 16×17 dot and 8×9 dot character font to display
the caption fonts.
Various character attributes
Character colors
: 16colors (analog mode: lVp-p output ) / 8colors (digital mode)
Character background colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode)
Fringe / shadow colors
: 16colors (analog mode: lVp-p output ) / 8colors (digital mode)
Full screen colors
: 16colors (analog mode: lVp-p output ) / 8colors (digital mode)
Italic character (slanting)
Attribute can be changed without spacing
Vertical display start line number can be set for each row independently (Rows can be overlapped)
Horizontal display start position can be set for each row independently
Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently
Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode
Ten character sizes *1
Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5)
(1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5)
Shuttering and scrolling on each row
Simplified Graphic Display
Note *1: range depends on display mode : refer to the manual for details.
„Data Slicer (closed caption format)
Closed caption data and XDS data extraction
NTSC/PAL, and extracted line can be specified
„Bus Cycle Time / Instruction-Cycle Time
Bus Cycle Time Instruction Cycle Time
Clock Divider
System Clock Oscillation
Internal VCO
(Ref: X'tal 32.768kHz)
Internal RC
Oscillation Frequency
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V

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Input / Output Ports
: 4 ports (23 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually: 3 ports (15 terminals)
„AD Converter
• 4 channels×6-bit AD converters
„Serial Interfaces
IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
„PWM Output
3 channels×7-bit PWM
Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
Base Timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow
(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
„Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal)
Noise rejection function
Polarity switching
„Watchdog Timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
„ROM Correction Function
Max 128 bytes / 2 addresses
12 sources 8 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Data slicer
7. Vertical synchronous signal interrupt (VS), horizontal line (HS)
8. IIC, Software
Interrupt Priority Control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or
highest priority can be set.

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„Sub-routine Stack Level
A maximum of 128 levels (stack is built in the internal RAM)
„Multiplication/Division Instruction
16 bits×8 bits (7 instruction cycle times)
16 bits÷8 bits (7 instruction cycle times)
„3 Oscillation Circuits
Built-in RC oscillation circuit used for the system clock
Built-in VCO circuit used for the system clock and OSD
X’tal oscillation circuit used for base timer, system clock and PLL reference
„Standby Function
HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
- Pull the reset terminal (RES) to low level.
- Feed the selected level to either P70/INT0 or P71/INT1.
MFP36SDJ (Lead-free type)
DIP36S (Lead-free type)
„Development Tools
Evaluation chip:
EVA86000 (main) + ECB863200A (evaluation chip board)
+ SUB863400A (sub board)
+ POD36-CABLE (cable)
+ POD36-DIP (for DIP36S)
or POD36-MFP (for MFP36SDJ)

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