LC8220 Datasheet PDF - Sanyo Semicon Device


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LC8220
Sanyo Semicon Device

Part Number LC8220
Description JPEG Still Color Image Compression/Decompression LSI
Page 13 Pages

LC8220 datasheet pdf
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Ordering number : EN*4909A
Preliminaly
CMOS LSI
LC8220
JPEG Still Color Image
Compression/Decompression LSI
Overview
The LC8220 JPEG LSI implements digital still image
compression and decompression conforming to the JPEG
(Joint Photographic Expert Group) standard. The LC8220
includes the baseline system of the ISO 10918 (JPEG)
standard, and requires no external components to construct
an application that performs JPEG compliant
compression/decompression.
Features
• Conforms to the ISO 10918-1 baseline system
• Four quantization tables and four Huffman tables (two
for AC and two for DC) are built in.
• Hardware support for JPEG marker codes
• Built-in bidirectional YUV - RGB converter
• Many color component sampling ratios are supported.
(e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.)
• Level shift function that can be defined for each
component
• Built-in dual buffers for reduced data transfer load
• Bus sizing function that allows direct connection to 8-,
16-, and 32-bit busses
• Endian control function
• Three independent data buses
Package Dimensions
unit: mm
3153A-QFP160
[LC8220]
SANYO: QFP160
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
32896HA (OT)/D1694TH (OT) No. 4909-1/13



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Block Diagram
The LC8220 has three independent buses.
LC8220
Pin Assignment
No. 4909-2/13



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Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Symbol
VSS
CTLCS
CTLRD
CTLWR
CTLRDY
CTLERR
CTLINT
CPUCTL
CTLSIZE
VDD
VSS
CTLA7
CTLA6
CTLA5
CTLA4
CTLA3
CTLA2
CTLA1
CTLA0
VDD
VSS
CTLD15
CTLD14
CTLD13
CTLD12
CTLD11
CTLD10
CTLD9
CTLD8
VDD
VSS
CTLD7
CTLD6
CTLD5
CTLD4
CTLD3
CTLD2
CTLD1
CTLD0
VDD
VSS
CLK
CLKSEL
RESET
TEST
TESTOUT
MDD10
MDD9
MDD8
VDD
VSS
MDD7
MDD6
MDD5
LC8220
I/O Function
— Ground
I Control bus chip select*2
I Control bus read request*3
I Control bus write request*4
O Control bus ready for read/write requests*5
O Error interrupt request
O Control bus interrupt request
I Connected CPU type setting for the control bus*1
I Bus width selection for the control bus (0: 8 bits, 1: 16 bits)
— +5 V power supply
— Ground
I
I
I
I
Control address bus
I
I
I
I
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Control data bus (D15 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Control data bus
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I System clock
I Clock divisor selection (0: no divisor, 1: divisor used)*6
I System reset
I Test mode selection (0: normal operation, 1: test mode)*6
O Test result output*8
I/O
I/O Test mode data bus*7
I/O
— +5 V power supply
— Ground
I/O
I/O Test mode data bus*7
I/O
Continued on next page.
No. 4909-3/13



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LC8220
Continued from preceding page.
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Symbol
MDD4
MDD3
MDD2
MDD1
MDD0
VDD
VSS
TESTI1
TESTI2
TESTI3
TESTI4
TESTI5
TESTO1
TESTO2
TESTI6
TESTO3
CPUPX
PXCS
PXRD
PXWR
PXRDY
PXINT
PXRLS
PXEND
(NC)
VDD
VSS
PXD31
PXD30
PXD29
PXD28
PXD27
PXD26
PXD25
PXD24
VDD
VSS
PXD23
PXD22
PXD21
PXD20
PXD19
PXD18
PXD17
PXD16
VDD
VSS
PXD15
PXD14
PXD13
PXD12
PXD11
PXD10
PXD9
PXD8
I/O Function
I/O
I/O
I/O Test mode data bus*7
I/O
I/O
— +5 V power supply
— Ground
I
I
I Test mode input pins*9
I
I
O
Test mode output pins*8
O
I Test mode input pin*9
O Test mode output pin*8
I Connected CPU type setting for the pixel bus*1
I Pixel bus chip select*2
I Pixel bus read request*3
I Pixel bus write request*4
O Pixel bus ready for read/write requests*5
O Pixel bus interrupt request
I Pixel bus interrupt release
O Pixel bus last data output indicator
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O Pixel data bus
I/O (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O Pixel data bus
I/O (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O Pixel data bus
I/O (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
Continued on next page.
No. 4909-4/13




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