K9GBG08U0B Datasheet PDF - Samsung


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K9GBG08U0B
Samsung

Part Number K9GBG08U0B
Description 32Gb B-die NAND Flash
Page 30 Pages

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SAMSUNG CONFIDENTIAL
Rev. 1.1, Sep. 2012
K9GBG08U0B
K9LCG08U0B
K9HDG08UXB
32Gb B-die NAND Flash
Multi-Level-Cell (2bit/cell)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2012 Samsung Electronics Co., Ltd. All rights reserved.
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K9GBG08U0B
K9LCG08U0B K9HDG08UXB
datasheet
SAMSUNG CONFIDENTIAL
Rev. 1.1
FLASH MEMORY
Revision History
Revision No.
History
0.0 1. Initial issue
0.1 1. Chpater 1.1 Features updated.
2. Chpater 1.2 Product List updated.
3. Chpater 1.3 General Description revised.
4. Chpater 1.4 Pin Configuration (48TSOP) updated.
5. Chpater 2.1 Absolute Maximum DC Rating added.
6. Chpater 2.2 Recommended Operating Conditions revised.
7. Chpater 2.3 DC And Operating Characteristics revised.
8. Chpater 2.4 Valid Block revised.
9. Chpater 2.5 AC Test Condition revised.
10. Chpater 2.6 Capacitance revised.
11 Chpater 2.8 Program / Erase Characteristics revised.
12.Chpater 2.10 AC Characteristics for Operation revised.
13.Chpater 4.26 00h Address ID Cycle revised.
14.Chpater 4.27 40h Address ID Cycle revised.
15.Chpater 5.18 Read Id revised.
0.11 1. Chapter 1.1 Features revised.
2. Chpater 1.2 Product List revised.
3. Chpater 1.3 General Description revised.
1.0 1. There is no change.
1.1 1. PartNumber(QDP) Added.
2.Chpater 1.5.1 Package Dimensions revised.
Draft Date Remark Edited by Reviewed by
Jul. 14, 2011 Target Y.E.Yoon Y.E.Yoon
Oct. 31, 2011 Target H.H.Shin H.K.Kim
Mar. 02, 2012 Target H.H.Shin H.K.Kim
Mar. 07, 2012
Sep, 04. 2012
Final
Final
H.H.Shin
H.H.Shin
H.K.Kim
H.K.Kim
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K9GBG08U0B
K9LCG08U0B K9HDG08UXB
datasheet
SAMSUNG CONFIDENTIAL
Rev. 1.1
FLASH MEMORY
Table Of Contents
1.0 INTRODUCTION ........................................................................................................................................................ 5
1.1 Features .................................................................................................................................................................. 5
1.2 Product List.............................................................................................................................................................. 5
1.3 General Description................................................................................................................................................. 5
1.4 Pin Configuration (48TSOP, Mono, DDP) .............................................................................................................. 6
1.4.1Package Dimensions ......................................................................................................................................... 6
1.5 Pin Configuration (48TSOP, QDP) .......................................................................................................................... 7
1.5.1Package Dimensions ......................................................................................................................................... 7
1.6 Pin Description ........................................................................................................................................................ 8
2.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
2.1 Absolute Maximum DC Rating ................................................................................................................................ 11
2.2 Recommended Operating Conditions ..................................................................................................................... 11
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) ................................... 11
2.4 Valid Block............................................................................................................................................................... 12
2.5 AC Test Condition ................................................................................................................................................... 12
2.6 Capacitance(TA=25°C, VCC=3.3V, f=1MHz) .......................................................................................................... 12
2.7 Mode Selection........................................................................................................................................................ 12
2.8 Program / Erase Characteristics.............................................................................................................................. 13
2.9 AC Timing Characteristics for Command / Address / Data Input ........................................................................... 13
2.10 AC Characteristics for Operation........................................................................................................................... 14
3.0 NAND FLASH TECHNICAL NOTES .......................................................................................................................... 15
3.1 Initial Invalid Block(s) ............................................................................................................................................... 15
3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 15
3.3 Error In Write or Read Operation............................................................................................................................. 16
3.4 Addressing For Program Operation......................................................................................................................... 18
3.5 System Interface Using CE don’t-care. ................................................................................................................... 20
4.0 TIMING DIAGRAMS ................................................................................................................................................... 21
4.1 Command Latch Cycle ............................................................................................................................................ 21
4.2 Address Latch Cycle................................................................................................................................................ 21
4.3 Input Data Latch Cycle ............................................................................................................................................ 22
4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)...................................................................................... 22
4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) ..................................................................... 23
4.6 Status Read Cycle .................................................................................................................................................. 23
4.7 Read Operation ...................................................................................................................................................... 24
4.8 Read Operation(Intercepted by CE) ....................................................................................................................... 24
4.9 Random Data Output In a Page ............................................................................................................................. 25
4.10 Cache Read Operation......................................................................................................................................... 26
4.11 Two-Plane Page Read Operation with Two-Plane Random Data Out ................................................................. 27
4.12 Two-Plane Cache Read Operation with Two-Plane Random Data Out (1/2)....................................................... 28
4.13 Two-Plane Cache Read Operation with Two-Plane Random Data Out (2/2)....................................................... 29
4.14 Page Program Operation...................................................................................................................................... 29
4.15 Page Program Operation with Random Data Input .............................................................................................. 30
4.16 Copy-Back Program Operation with Random Data Input ..................................................................................... 31
4.17 Intelligent Copy-Back Program(1/2) ..................................................................................................................... 32
4.18 Cache Program Operation(available only within a block) ..................................................................................... 34
4.19 Two-Plane Copy-Back Program ............................................................................................................................ 35
4.20 Two-Plane Intelligent Copy-Back Program(1/3) .................................................................................................... 36
4.21 Two-Plane Page Program Operation .................................................................................................................... 39
4.22 Two-Plane Cache Program Operation ................................................................................................................ 40
4.23 Block Erase Operation.......................................................................................................................................... 41
4.24 Two-Plane Block Erase Operation ....................................................................................................................... 42
4.25 Read ID Operation................................................................................................................................................ 43
4.26 00h Address ID Cycle............................................................................................................................................ 43
4.27 40h Address ID Cycle............................................................................................................................................ 43
5.0 DEVICE OPERATION ................................................................................................................................................ 46
5.1 Page Read.............................................................................................................................................................. 46
5.2 Cache Read............................................................................................................................................................ 47
5.3 Two-plane Page Read............................................................................................................................................. 49
5.4 Two-plane Cache Read .......................................................................................................................................... 50
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K9GBG08U0B
K9LCG08U0B K9HDG08UXB
datasheet
SAMSUNG CONFIDENTIAL
Rev. 1.1
FLASH MEMORY
5.5 Page Program ......................................................................................................................................................... 51
5.6 Copy-back Program................................................................................................................................................ 52
5.7 Intelligent Copy-Back Program ................................................................................................................................ 53
5.8 Cache Program ....................................................................................................................................................... 54
5.9 Register Read Out Mode 1..................................................................................................................................... 57
5.10 Two-plane Register Read Out Mode 1 ................................................................................................................. 57
5.11 Two-plane Page Program..................................................................................................................................... 58
5.12 Two-plane Copy-back Program ............................................................................................................................. 59
5.13 Two-Plane Intelligent Copy-back Program(1/2)..................................................................................................... 62
5.14 Two-plane Cache Program................................................................................................................................... 65
5.15 Block Erase ........................................................................................................................................................... 66
5.16 Two-plane Block Erase......................................................................................................................................... 66
5.17 Read Status........................................................................................................................................................... 67
5.18 Read Id ................................................................................................................................................................. 68
5.19 Reset .................................................................................................................................................................... 69
5.20 Output driver setting ............................................................................................................................................. 69
5.21 Ready/busy............................................................................................................................................................ 71
6.0 DATA PROTECTION & POWER UP SEQUENCE.................................................................................................... 72
6.1 WP AC Timing guide .............................................................................................................................................. 73
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