K4D261638K-LC50 Datasheet PDF - Samsung


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K4D261638K-LC50
Samsung

Part Number K4D261638K-LC50
Description 128Mbit GDDR SDRAM
Page 18 Pages

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K4D261638K
128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.3
July 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 /19 -
Rev. 1.3 July 2007



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K4D261638K
Revision History
Revision Month
Year
0.0
January
2006
1.0 September 2006
1.1
October
2006
1.2 November 2006
1.3 July 2007
History
- Target Spec
- Defined target specification
- Added the Current Spec
- Added the IBIS Data
- Added and Revised the IBIS Data
- Added power up comment
- Revised voltage comment of power up sequence
128M GDDR SDRAM
- 2 /19 -
Rev. 1.3 July 2007



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K4D261638K
128M GDDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
1.0 FEATURES
• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 2,3(clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going
edge of the system clock
• Differential clock input
• Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• Lead free 66pin TSOP-II (RoHS compliant)
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
2.0 ORDERING INFORMATION
Part NO.
Max Freq.
K4D261638K-LC40
250MHz
K4D261638K-LC50
200MHz
* K4D261638K-TC is the Leaded package part number.
* For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V.
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
SSTL_2
Package
66pin TSOP-II
3.0 GENERAL DESCRIPTION
FOR 2M x 16Bit x 4 Bank DDR SDRAM
The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fab-
ricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
- 3 /19 -
Rev. 1.3 July 2007



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K4D261638K
4.0 PIN CONFIGURATION (Top View)
128M GDDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66 PIN TSOP(II) 57
11 (400mil x 875mil) 56
12 (0.65 mm Pin Pitch) 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
CAS
Column Address Strobe
WE Write Enable
L(U)DQS
Data Strobe
L(U)DM
RFU
Data Mask
Reserved for Future Use
BA0, BA1
A0 ~A11
DQ0 ~ DQ15
VDD
VSS
VDDQ
VSSQ
NC
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ’s
Ground for DQ’s
No Connection
- 4 /19 -
Rev. 1.3 July 2007




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