K3P6C2000B-SC Datasheet PDF - Samsung semiconductor

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K3P6C2000B-SC
Samsung semiconductor

Part Number K3P6C2000B-SC
Description 32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM
Page 4 Pages


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K3P6C2000B-SC
CMOS MASK ROM
32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM
FEATURES
Switchable organization
2,097,152 x 16(word mode)
1,048,576 x 32(double word mode)
Fast access time
Random Access : 100ns(Max.)
Page Access : 30ns(Max.)
4 double words/ 8 words page access
Current consumption
Operating : 150mA(Max.)
Standby : 50µA(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3P6C2000B-SC : 70-SSOP-500
GENERAL DESCRIPTION
The K3P6C2000B-SC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 2,097,152x16 bit(word mode) or as
1,048,576x32 bit(double word mode) depending on WORD
voltage level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 double words(or 8 words) of data to read fast in the
same page, CE and A2 ~ A19 should not be changed.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P6C2000B-SC is packaged in a 70-SSOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A19
.
.
.
.
.
.
.
.
A2
A0~A1
A-1
CE
OE
WORD
X
BUFFERS
AND
DECODER
Y
BUFFERS
AND
DECODER
CONTROL
LOGIC
MEMORY CELL
MATRIX
(1,048,576x32/
2,097152x16)
SENSE AMP.
DATA OUT
BUFFERS
...
Q0/Q16 Q15/Q31
Pin Name
A0 - A1
A2 - A19
Q0 - Q30
Q31 /A-1
WORD
CE
OE
VCC
VSS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 31(Double word mode)/
LSB Address(Word mode)
Double word/Word mode selection
Chip Enable
Output Enable
Power (+5V)
Ground
No Connection
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
VCC
7
Q0 8
Q16 9
Q1 10
Q17 11
VSS 12
VCC 13
Q2 14
Q18 15
Q3 16
Q19 17
Q4 18
Q20 19
Q5 20
Q21 21
VSS 22
VCC 23
Q6 24
Q22 25
Q7 26
Q23 27
VSS 28
A6 29
A7 30
A8 31
A9 32
A10 33
A11 34
A12 35
SSOP
70 N.C
69 N.C
68 N.C
67 WORD
66 OE
65 CE
64 VSS
63 Q31/A-1
62 Q15
61 Q30
60 Q14
59 VSS
58 VCC
57 Q29
56 Q13
55 Q28
54 Q12
53 Q27
52 Q11
51 Q26
50 Q10
49 VSS
48 VCC
47 Q25
46 Q9
45 Q24
44 Q8
43 VCC
42 A19
41 A18
40 A17
39 A16
38 A15
37 A14
36 A13
K3P6C2000B-SC
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K3P6C2000B-SC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
Symbol
VIN
TBIAS
TSTG
Rating
-0.3 to +7.0
-10 to +85
-55 to +150
Unit
V
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Symbol
Min
Typ
Max
Supply Voltage
VCC 4.5 5.0 5.5
Supply Voltage
VSS 0 0 0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
ICC
ISB1
ISB2
ILI
ILO
VIH
VIL
VOH
VOL
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
VOUT=0 to VCC
IOH=-400µA
IOL=2.1mA
Min Max
- 150
-1
- 50
- 10
- 10
2.2 VCC+0.3
-0.3 0.8
2.4 -
- 0.4
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
Unit
mA
mA
µA
µA
µA
V
V
V
V
MODE SELECTION
CE OE
HX
LH
LL
WORD
X
X
H
L
Q31/A-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operating
Data
High-Z
High-Z
Q0~Q31:Dout
Q0~Q15 : Dout
Q16~Q30 : Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
COUT
CIN
NOTE : Capacitance is periodically sampled and not 100% tested.
Test Conditions
VOUT=0V
VIN=0V
Min
-
-
Max Unit
12 pF
12 pF
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K3P6C2000B-SC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to 70°C, VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
0.6V to 2.4V
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
Item
Symbol
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
tRC
tACE
tAA
tPA
tOE
tDF
tOH
NOTE : Page Address is determined as below.
Double word mode (WORD=VIH) ; A0, A1
Word mode (WORD=VIL) ; A -1, A0, A1
K3P6C2000B-SC10
Min Max
100
100
100
30
30
20
0
K3P6C2000B-SC12
Min Max
120
120
120
50
50
20
0
K3P6C2000B-SC15
Min Max
150
150
150
70
70
30
0
Unit
ns
ns
ns
ns
ns
ns
ns
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K3P6C2000B-SC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
A0~A19
A-1(*1)
CE
OE
DOUT
D0~D15
D16~D31(*2)
PAGE READ
ADD1
tACE
tRC
tOE
VALID DATA
ADD2
tAA
tOH
VALID DATA
tDF(*3)
CE
tDF(*3)
OE
ADD
A2~A19
ADD
A0,A1
A -1(*1)
DOUT
D0~D15
D16~D31(*2)
1 st
tAA
2 nd
tPA
3 rd
VALID DATA
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1. Word Mode only. A-1 is Least Significant Bit Address.(WORD = VIL)
*2. Double Word Mode only.(WORD = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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K3P6C2000B-SC 32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM K3P6C2000B-SC
Samsung semiconductor
K3P6C2000B-SC pdf

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