ISL6615A Datasheet PDF - Intersil Corporation


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ISL6615A
Intersil Corporation

Part Number ISL6615A
Description High-Frequency 6A Sink Synchronous MOSFET Drivers
Page 12 Pages

ISL6615A datasheet pdf
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High-Frequency 6A Sink Synchronous MOSFET
Drivers with Protection Features
ISL6615A
The ISL6615A is a high-speed MOSFET driver optimized
to drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. This
driver, combined with an Intersil Digital or Analog
multiphase PWM controller, forms a complete high
frequency and high efficiency voltage regulator.
The ISL6615A drives both upper and lower gates over a
range of 4.5V to 13.2V. This drive-voltage provides the
flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
The ISL6615A features 6A typical sink current for the
low-side gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the
lower MOSFET due to the high dV/dt of the switching
node.
An advanced adaptive zero shoot-through protectionis
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the
dead-time. The ISL6615A includes an overvoltage
protection feature opear tional before VCC exceeds its
turn-on threshold,at which the PHASE node is connected
to the gate of the low side MOSFET (GL ATE). The output
voltage of the converter is then limited by the threshold
of the low side MOSFET, which provides some protection
to the load if the upper MOSFET(s) is shorted.
The ISL6615A also features aninput that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevennt egative
transients on the controlled outputvoltage when
operation is suspended. Thsi feature eliminates the need
for the Schottkydiode that may be utilized in apower
system to protect the load from negative output voltage
damage.
Features
• Dual MOSFET Drives for Synchronous Rectified
Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
-L GATE Detection
-A uto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 5V PWM Input Logic
• Tri-State PWM Input for Safe Output StageShutdown
• Tri-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat
Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-free (RoHS compliant)
Applications*(see page 10)
• Optimized for POL DC/DC Converters for IBA
Systems
• Core Regulators for Intel® and AMD®
Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power
Supplies
Related Literature*(see page 10)
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface MountDevices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QNF Packages”
April 22, 201 0
FN6608 .1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
http://www.Datasheet4U.com
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.



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Block Diagram
ISL6615A
ISL6615A
VCC
PWM
(UVCC)
+5V
PRE-POR OVP
FEATURES
10k
8k
POR/
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
(LVCC)
SUBSTRATE RESISTANCE
BOOT
UGATE
PHASE
PVCC
UVCC = PVCC
LGATE
GND
PAD
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
Typical Application - 2 Channel Converter
+5V
PGOOD
VID
(OPTIONAL)
+5V
FB COMP
VCC
VSEN
PWM1
PWM2
PWM
CONTROL
(ISL63xx
OR ISL65xx)
ISEN1
ISEN2
FS/EN
GND
+7V TO +13.2V
PVCC
BOOT
VCC
UGATE
PWM
ISL6615A
PHASE
LGATE
GND
VIN
+7V TO +13.2V
PVCC
BOOT
VCC
UGATE
PWM
ISL6615A
PHASE
GND
LGATE
VIN
+VCORE
THE ISL6615A CAN SUPPORT 5V PWM INPUT
2 FN6608.1
April 22, 2010



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ISL6615A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6615ACBZ
6615A CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6615ACRZ
615A
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6615AIBZ
6615A IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6615AIRZ
15AI
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL6615AFRZ
15AF
-40 to +125
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6615A. For more information on MSL please
see techbrief TB363.
Pin Configurations
ISL6615A
(8 LD SOIC)
TOP VIEW
ISL6615A
(10 LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 PVCC
6 VCC
5 LGATE
UGATE 1
BOOT 2
N/C 3
PWM 4
GND 5
GND
10 PHASE
9 PVCC
8 N/C
7 VCC
6 LGATE
COMMAND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Functional Pin Descriptions
PACKAGE PIN
#
SOIC DFN
11
22
- 3, 8
34
45
56
67
79
8 10
9 11
PIN
SYMBOL
FUNCTION
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this
pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.
See the Internal Bootstrap Device “TIMING DIAGRAM” on page 6 under Description for guidance in
choosing the capacitor value.
N/C No Connection. Recommend to connect pin 3 to GND andpin 8 to PVCC.
PWM
The PWM signal isthe control inputfor the driver. The PWM signal can enter three distinct states during
operation, see the“TIMING DIAGRAM” on page 6 section under Description for further details. Connect
this pin to the PWM output of the controller.
GND
Bias and reference ground. Al signals are referenced to this node. It is also the power ground return
of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin
to GND.
PVCC
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V.
Place a high quality low ESR ceramic capacitor from this pin to GND.
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin
provides a return path for the upper gate drive.
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
3 FN6608.1
April 22, 2010



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ISL6615A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . .VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . 36V
Input Voltage (VPWM). . . . . . . . . . . . . . . .GND - 0.3V to 7V
UGATE . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
. . . . GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . .GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to
. . . . . . . . . . . . . . . . . . 30V (<200ns, VBOOT-GND < 36V))
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance . . . . . . . . . . . . . . θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 4) . . . . . . . . . . 98
N/A
DFN Package (Notes 5, 6) . . . . . . . . 47
5
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6615ACRZ, ISL6615ACBZ. . . . . . . . . . . . 0°C to +70°C
ISL6615AIRZ, ISL6615AIBZ . . . . . . . . . . -40°C to +85°C
ISL6615AFRZ (Note 7) . . . . . . . . . . . . . -40°C to +125°C
Maximum Operating Junction Temperature. . . . . . . . +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
PVCC Supply Voltage . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. When using ISL6615AFRZ, care should be taken to minimize power dissipation.
Electrical Specifications Recommended Operating Conditions; Boldface limits apply over the operating
temperature ranges.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
IVCC
IPVCC
fPWM = 300kHz, VVCC = 12V
fPWM = 300kHz, VPVCC = 12V
- 4.5 -
-8-
mA
mA
VCC Rising Threshold
6.1 6.4 6.7
V
VCC Falling Threshold
4.7 5.0 5.3
V
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
PWM Rising Threshold (Note 9)
IPWM
VPWM = 5V
VPWM = 0V
VCC = 12V
- 510 -
- -475 -
- 3.00 -
µA
µA
V
PWM Falling Threshold (Note 9)
VCC = 12V
- 2.00 -
V
Typical Tri-State Shutdown Window
VCC = 12V
1.80 - 2.40
V
Tri-State Lower Gate Falling
Threshold
VCC = 12V
- 1.50 -
V
Tri-State Lower Gate Rising
Threshold
VCC = 12V
- 1.00 -
V
Tri-State Upper Gate Rising
Threshold
VCC = 12V
- 3.20 -
V
Tri-State Upper Gate Falling
Threshold
VCC = 12V
- 2.70 -
V
Shutdown Holdoff Time
tTSSHD
-5 5-
ns
4 FN6608.1
April 22, 2010




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