ILA1062 Datasheet PDF - IK Semiconductor

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ILA1062
IK Semiconductor

Part Number ILA1062
Description TELEPHONE SPEECH NETWORK
Page 9 Pages


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TECHNICAL DATA
TELEPHONE SPEECH NETWORK
WITH DIALER INT`ERFACE
ILA1062/1062A
FEATURES
PIN CONNECTION
- Low DC line voltage; operates down to 1.6V (excluding
polarity guard)
- Voltage regulator with adjustable static resistance
- Provides a supply for external circuits
- Symmetrical high-impedance inputs (64 kΩ) for
dynamic, magnetic or piezo-electric microphones
- Asymmetrical high-impedance input (32 kΩ) for electret
microphones
- DTMF signal input with confidence tone
- Mute input for pulse or DTMF dialing
- ILA1062: active HIGH (MUTE)
- ILA1062A: active LOW (MUTE)
- Receiving amplifier for dynamic, magnetic or
piezo-electric earpieces
- Large gain setting range on microphone and earpiece
amplifiers
- Line loss compensation (line current dependent) for
microphone and earpiece amplifiers
- Gain control curve adaptable to exchange supply
- DC line voltage adjustment facility
DESCRIPTION
LN 1
GAS1 2
GAS2 3
OR 4
GAR 5
MIC- 6
MIC+ 7
STAB 8
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ILA1062
or
BILTA11006622AA
16 SLPE
15 AGC
14 REG
13 VCC
12 MUTE
11 DTMF
10 IR
9 VEE
The ILA1062 and ILA1062A are integrated circuits that perform all speech and line interface functions required in fully
electronic telephone sets. They perform electronic switching between dialing and speech. The ICs operates at line voltage down
to 1.6 V DC (with reduced performance) to facilitate the use of more telephone sets connected in parallel.
All statements and values refer to all versions unless otherwise specified. The ILA1062 (ILA1062A) is packaged in a standard
16-pin plastic DIP and special plastic DIP with internal heatsink is also available.
QUICK REFERENCE DATA
Characteristic
Line Voltage
Operating Line Current
Normal Operation
with Reduced Performance
Internal Supply Current
Supply Voltage for Peripherals
Symbol
VLN
I line
I CC
VCC
Voltage Gain
microphone amplifier
receiving amplifier
Line loss compensation
Gain Control
Exchange Supply Voltage
Exchange Feeding bridge Resistance
GV
ΔGV
Vexch
Rexch
Test Condition
Iline = 15mA
VCC = 2.8V
Iline= 15mA
Ip= 1.2mA
Ip= 0mA
Min
Typ
Max
Unit
3.55 4.0 4.25 V
2.0 Vdc
11 140 mA
1 11 mA
0.9 1.35 mA
V
2.2 2.7
2.2 3.4
44 52 dB
20 31 dB
5.8 dB
36 60 V
0.4 1 kΩ



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ILA1062/1062A
BLOCK DIAGRAM
VCC
13
IR 10
BILTA11006622AA
LN
1
5
GAR
-
4 QR
+
MIC+
MIC-
7
6
+
-
-
DTMF
(1)
MUTE
11 dB
12
SUPPLY AND
REFERENCE
+
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-
+
CONTROL
CURRENT
LOW VOLTAGE
CIRCUIT
9
VEE
CURRENT
REFERENCE
14 15
8
REG AGC
STAB
(1) Pin 12 is active HIGH (MUTE) for ILA1062.
2 GAS1
3 GAS2
16
SLPE
Fig.1 Block diagram for ILA1062A



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ILA1062/1062A
FUNCTIONAL DESCRIPTION
Supplies VCC, LN, SLPE, REG and STAB
Power for the IC and its peripheral circuits is usually obtained from
the telephone line. The supply voltage is delivered from the line via a
dropping resistor and regulated by the IC. The supply voltage VCC
may also be used to supply external circuits e.g. dialing and control
circuits.
Decoupling of the supply voltage is performed by a capacitor
between VCC and VEE . The internal voltage regulator is decoupled by
a capacitor between REG and VEE.
The DC current flowing into the set is determined by the exchange
supply voltage Vexch , the feeding bridge resistance Rexch and the DC
resistance of the telephone
line Rline .
The circuit has internal current stabilizer operating at a level
determined by a 3.6 kΩ resistor connected between STAB and VEE
(see Fig.6). When the line current (Iline) is more than 0.5mA greater
than the sum of the IC supply current (ICC) and the current drawn by
the peripheral circuitry connected to VCC (Ip) the excess current is
shunted to VEE via LN.
At line currents below 9mA the internal reference voltage is
automatically adjusted to a lower value (typically 1.6V at 1mA). This
means that more sets can be operated in parallel with DC line voltage
(excluding the polarity guard) down to an absolute minimum voltage
of 1.6V. At line currents below 9mA the circuit has limited sending
and receiving levels. The internal reference voltage can be adjusted
by means of an external resistor (RVA). This resistor when connected
between LN and REG will decrease the internal reference voltage
and when connected between REG and SLPE will increase the
internal reference voltage.
Microphone inputs MIC+ and MIC- and gain pins
GAS1 and GAS2
The circuit has symmetrical microphone inputs. Its input impedance
is 64 kΩ (2 x 32kΩ) and its voltage gain is typically 52 dB (when R7
= 68k?; see Fig.6).
Dynamic, magnetic, piezo-electric or electret (with built-in FET
source followers) can be used.
The gain of the microphone amplifier can be adjusted between 44 dB
and 52 dB to suit the sensitivity of the transducer in use. The gain is
proportional to the value of R7 which is connected between GAS1
and GAS2.
The regulated voltage on the line terminal (VLN) can be calculated as:
Stability is ensured by two external capacitors, C6 connected
VLN = Vref + ISLPE x R9
VLN = Vref + {(Iline - ICC - 0.5 x 10-3A) - Ip} x R9
between GAS1 and SLPE and C8 connected between GAS1 and
VEE. The value of C6 is 100pF but this may be increased to obtain a
first-order low-pass filter. The value of C8 is 10 times the value of
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Vref is an internally generated temperature compensated reference
C6. The cut-off frequency corresponds to the time constant R7 x C6.
voltage of 3.7V and R9 is an external resistor connected between
SLPE and VEE.
Input MUTE (ILA1062A)
In normal use the value of R9 would be 20?.
Changing the value of R9 will also affect microphone gain, DTMF
gain, gain control characteristics, sidetone level, maximum output
swing on LN and the DC characteristics (especially at the lower
voltages).
When MUTE is LOW or open-circuit, the DTMF input is enable and
the microphone and receiving amplifier inputs are inhibited. The
reverse is true when MUTE is HIGH.
MUTE switching causes only negligible clicking on the line and
earpiece output. If the number of parallel sets in use causes a drop in
line current to below 6 mA the DTMF amplifier becomes active
independent to the DC level applied to the MUTE input.
Fig.2 Equivalent impedance circuit
Dual-tone multi-frequency input DTMF
When the DTMF input is enable dialing tones may be sent on to the
line. The voltage gain from DTMF to LN is typically 25.5 dB (when
R7=68kΩ) and varies with R7 in the same way as the microphone
gain. The signalling tones can be heard in the earpiece at a low level
(confidence tone).
Under normal conditions, when ISLPE >>ICC + 0.5mA + Ip, the static
behaviour of the circuit is that of a 3.7V regulator diode with an
internal resistance equal to that of R9. In the audio frequency range
the dynamic impedance is largely determined by R1. Fig.2 show the
equivalent impedance of the circuit.
Receiving amplifier IR, QR and GAR
The receiving amplifier has one input (IR) and a non-inverting output
(QR). The IR to QR gain is typically 31dB (when R4 = 100kΩ). It
can be adjusted between 20 and 31dB to match the sensitivity of the
transducer in use. The gain is set with the value of R4 which is
connected between GAR and QR. The overall receive gain, between
LN and QR, is calculated by subtracting the anti-sidetone network
attenuation (32dB) from the amplifier gain. Two external capacitors,
C4 and C7, ensure stability. C4 is normally 100pF and C7 is 10 times
the value of C4. The value of C4 may be increased to obtain a first-
order low-pass filter. The cut-off frequency will depend on the time
constant R4 x C4.
The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will be higher
under speech conditions where the peak to RMS ratio is higher.



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Automatic gain control input AGC
Automatic line loss compensation is achieved by connecting a
resistor (R6) between AGC and VEE.
The automatic gain control varies the gain of the microphone
amplifier and the receiving amplifier in accordance with the DC line
current. The control range is 5.8 dB which corresponds to a line
length of 5 km for a
0.5mm diameter twisted-pair copper cable with a DC resistance of
176 ?/km and average attenuation of
1.2dB/km. Resistor R6 should be chosen in accordance with the
exchange supply voltage and its feeding bridge resistance. The ratio
of start and stop currents of the AGC curve is independent of the
value of R6. If no automatic
line-loss compensation is required the AGC pin may be left open-
circuit. The amplifiers, in this condition, will give their maximum
specified gain.
Sidetone suppression
The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and Zbal
suppresses the transmitted signal in the earpiece. Maximum
compensation is obtained when the following conditions are fulfilled:
R 8 x Zbal
R9 x R2 = R1 x R 3 + ⎝⎜ R 8 + Zbal ⎠⎟
(1)
Zbal
Zline
=
Zbal + R 8 Zline+ R 1
ILA1062/1062A
(2)
If fixed values are chosen for R1, R2, R3 and R9, then condition (1)
will always be fulfilled when
To obtain optimum sidetone suppression, condition (2) has to be
fulfilled which results in:
R8
Zbal =
x Zline = k x Zline
R1
R8
Where k is scale factor; k =
R1
The scale factor k, dependent on the value of R8, is chosen to meet
the following criteria:
- compatibility with a standard capacitor from the E6 or
E12 range for Zbal
- |Zbal//R8|<<R8 fulfilling condition (a) and thus
ensuring correct
anti-sidetone bridge operation
- |Zbal + R8|>>R9 to avoid influencing the transmit gain.
In practise Zline varies considerably with the line type and length. The
value chosen for Zbal should therefore be for an average line thus
giving optimum setting for short or long lines.
ABSOLUTE MAXIMUM RATING
Characteristic
Positive Continuous Line Voltage
Repetitive Line Voltage During Switch-on
or Line Interruption
Repetitive Peak Line Voltage for a 1ms
Pulse per 5s
Line Current
Input Voltage on all other Pins
Total Power
Standard DIP
Dissipation
DIP with heatsink
Operating Ambient Temperature
Storage Temperature
Junction Temperature
Symbol
VLN
VLN(R)
VLN(RM)
Iline
VI
Ptot
TA
Tstg
Tj
Test Condition
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R9 = 20Ω; R10 = 13Ω;
see Fig.6
R9 = 20Ω; note 1
R9 = 20Ω; note 2
Min Typ Max Unit
12 V
13.2 V
28 V
140 mA
-0.7
VCC+0.7
V
0.58 W
0.67
-25 +75 oC
-40
+125
oC
+125
oC
Notes
1. Mostly dependent on the maximum required TA and on the voltage between LN and SLPE.
2. Calculated for the maximum ambient temperature specified and a maximum junction temperature of 125oC.
(Thermal Resistance RJA = 85oC/W for standard DIP and RJA = 75oC/W for special DIP with heatsink).
150
ILN (mA)
130
(1) TA = 45oC; Ptot = 0.94 W
(2) TA = 55oC; Ptot = 0.82 W
(3) TA = 65oC; Ptot = 0.71 W
(4) TA = 75oC; Ptot = 0.58 W
110
(1)
90
(2)
70 (3) (1) TA = 45oC; Ptot = 1.07 W
50
(4) (2) TA = 55oC; Ptot = 0.93 W
(3) TA = 65oC; Ptot = 0.80 W
30 (4) TA = 75oC; Ptot = 0.67 W
2 4 6 8 10 12
VLN - VSLPE (V)
150
ILN (mA)
130
110 (1)
90 (2)
(3)
70
(4)
50
30
2 4 6 8 10 12
VLN - VSLPE (V)
Fig.3a Safe operating area
(Standard DIP)
Fig.3b Safe operating area
(DIP with HS)



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