IDT70V9379L Datasheet PDF - IDT


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IDT70V9379L
IDT

Part Number IDT70V9379L
Description HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Page 15 Pages

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HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9379L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x Low-power operation
– IDT70V9379L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
4ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x LVTTL- compatible, single 3.3V (±0.3V) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 128-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4857 drw 01
©2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-4857/2



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IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9379 is a high-speed 32K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
With an input data register, the IDT70V9379 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 500mW of power.
Pin Configuration(1,2,3)
NC
NC
NC
NC
A9R
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
GND
VCC
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9379PRF
PK-128-1(4)
128-Pin TQFP
Top View(5)
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.422
102 I/O12R
101 I/O11R
100 GND
99 NC
98 I/O10R
97 I/O9R
96 I/O8R
95 I/O7R
94 VCC
93 I/O6R
92 I/O5R
91 I/O4R
90 GND
89 I/O3R
88 VCC
87 I/O2R
86 I/O1R
85 I/O0R
84 GND
83 VCC
82 I/O0L
81 I/O1L
80 GND
79 I/O2L
78 I/O3L
77 GND
76 I/O4L
75 I/O5L
74 I/O6L
73 I/O7L
72 VCC
71 I/O8L
70 I/O9L
69 I/O10L
68 NC
67 VCC
66 I/O11L
65 I/O12L
4857 drw 02



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IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
Chip Enables
Read/Write Enable
OEL OER Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLKR
Clock
UBL
LBL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
UBR
LBR
ADSR
CNTENR
CNTRSTR
FT/PIPER
Upper Byte Select
Lower Byte Select
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
VCC Power
GND Ground
4857 tbl 01
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 UB LB R/W
Upper Byte
I/O9-17
Lower Byte
I/O0-8
MODE
X HX X X X
High-Z
High-Z
DeselectedPower Down
XX LXXX
High-Z
High-Z
DeselectedPower Down
XL HHHX
High-Z
High-Z
Both Bytes Deselected
XL HL HL
DATAIN
High-Z
Write to Upper Byte Only
XL HHL L
High-Z
DATAIN
Write to Lower Byte Only
XLHLL L
DATAIN
DATAIN
Write to Both Bytes
LL HLHH
DATAOUT
High-Z
Read Upper Byte Only
LL HHL H
High-Z
DATAOUT
Read Lower Byte Only
LL HL L H
DATAOUT
DATAOUT
Read Both Bytes
HX L HL L X
High-Z
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4857 tbl 02
6.432



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IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2,6)
Previous Addr
Address Address Used CLK ADS CNTEN CNTRST
I/O(3)
MODE
X X 0 X X L DI/O(0) Counte r Reset to Address 0
An X An L(4) X H DI/O(n) External Address Loaded into Counter
An Ap Ap H H
H DI/O(p) External Address BlockedCounter disabled (Ap reused)
X
Ap Ap + 1
H
L(5)
H DI/O(p+1) Counter EnabledInternal Address generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
4857 tbl 03
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage(1) Conditions
Grade
Ambient
Temperature(2)
GND
Vcc
Commercial
0OC to +70OC 0V 3.3V + 0.3V
Industrial
-40OC to +85OC
0V
3.3V + 0.3V
NOTES:
4857 tbl 04
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
Symbol
Parameter
VCC Supply Voltage
GND Ground
VIH Input High Voltage
VIL Input Low Voltage
Min.
3.0
0
2.0V
-0.3(1)
Typ.
3.3
0
____
____
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VCC +0.3V.
Max. Unit
3.6 V
0V
VCC+0.3V(2)
V
0.8 V
4857 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
VTERM(2)
Terminal Voltage
with Respect to
GND
Commercial
& Industrial
-0.5 to +4.6
Unit
V
TBIAS Temperature
Under Bias
TSTG Storage
Temperature
-55 to +125
-55 to +150
oC
oC
IOUT DC Output Current
50 mA
NOTES:
4857 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 0.3V.
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Parameter
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT(3) Output Capacitance
VOUT = 3dV
10 pF
NOTES:
4857 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
6.442




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