IDT70V9359L Datasheet PDF - IDT


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IDT70V9359L
IDT

Part Number IDT70V9359L
Description HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Page 16 Pages

IDT70V9359L datasheet pdf
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HIGH-SPEED 3.3V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9359/49L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9359/49L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin Fine Pitch Ball Grid Array (fpBGA) packages.
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A12L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1b 0b b a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a a b0b 1b 0/1
Counter/
Address
Reg.
NOTE:
1. A12 is a NC for IDT70V9349.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A12R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5638 drw 01
©2003 Integrated Device Technology, Inc.
1
AUGUST 2003
DSC-5638/3



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IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9359/49 is a high-speed 8/4K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
With an input data register, the IDT70V9359/49 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 450mW of power.
Pin Configurations(1,2,3,4)
07/03/02
Index
A9L
A10L
A11L
A12L(1)
NC
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VDD
FT/PIPEL
I/O17L
I/O16L
VSS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1 100
99 98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10
70V9359/49PF
66
11
PN100-1(5)
65
12
100-Pin TQFP
64
13
Top View(6)
63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R
A9R
A10R
A11R
A12R(1)
NC
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
VSS
OER
FT/PIPER
I/O17R
VSS
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
.
5638 drw 02
NOTES:
1. A12 is a NC for IDT70V9349.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.422



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IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(cont'd)(1,2,3,4)
70V9359/49BF
BF100(5)
07/03/02
100-Pin fpBGA
Top View(6)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10
A8R A11R UBR CNTRSTR Vss Vss Vss I/O13R I/O10R I/O17R
B1 B2 B3 B4 B5 B6 B7
B8 B9 B10
A6R A7R A10R A12R(1) R/WR OER PL/FTR I/O12R I/O9R I/O6R
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
A3R A4R A5R A9R CE1R I/O16R I/O15R I/O11R I/O7R I/O3R
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A0R CLKR A1R A2R LBR CE0R I/O14R I/O8R I/O5R I/O1R
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
Vss ADSR CNTENR A1L ADSL Vss I/O4R I/O2R I/O0R VDD
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Vss CLKL A0L A3L VDD Vss VDD I/O2L I/O1L I/O0L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
CNTENL A4L A7L UBL Vss I/O13L NC I/O4L Vss I/O3L
H1 H2 H3 H4 H5
H6 H7 H8 H9 H10
A2L A6L A11L CE0L CNTRSTL I/O15L I/O9L I/O7L I/O6L I/O5L
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
A5L A9L A12L(1) R/WL OEL PL/FTL I/O12L I/O10L Vss I/O8L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
A8L A10L LBL CE1L VDD VDD I/O16L I/O14L I/O11L I/O17L
5638 drw 03
NOTES:
1. A12 is a NC for IDT70V9349.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
,
6.432



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IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A12L(1)
OER
A0R - A12R(1)
I/O0L - I/O17L
I/O0R - I/O17R
CLKL
CLKR
UBL UBR
LBL LBR
ADSL
ADSR
CNTENL
CNTENR
CNTRSTL
CNTRSTR
FT/PIPEL
FT/PIPER
VDD
VSS
Names
Chip Enables(3)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Upper Byte Select(2)
Lower Byte Select(2)
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
5638 tbl 01
NOTE:
1. A12 is a NC for IDT70V9349.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0(5) CE1(5) UB(4) LB(4) R/W
Upper Byte
I/O9-17
Lower Byte
I/O0-8
MODE
X HX X X X
High-Z
High-Z
Deselected–Power Down
XX LXXX
High-Z
High-Z
Deselected–Power Down
XL HHHX
High-Z
High-Z
Both Bytes Deselected
XL HL HL
DATAIN
High-Z
Write to Upper Byte Only
XL HHL L
High-Z
DATAIN
Write to Lower Byte Only
XL HL L L
DATAIN
DATAIN
Write to Both Bytes
LL HL HH
DATAOUT
High-Z
Read Upper Byte Only
LL HHL H
High-Z
DATAOUT
Read Lower Byte Only
LL HL L H
DATAOUT
DATAOUT
Read Both Bytes
HX L HX X X
High-Z
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4 LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when
FT/PIPE = VIH,
5638 tbl 02
i.e. the signals take two cycles to deselect.
6.442




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