IDT70V7599S Datasheet PDF - IDT


www.Datasheet-PDF.com

IDT70V7599S
IDT

Part Number IDT70V7599S
Description HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
Page 22 Pages

IDT70V7599S datasheet pdf
View PDF for PC
IDT70V7599S pdf
View PDF for Mobile


No Preview Available !

HIGH-SPEED 3.3V 128K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
IDT70V7599S
Features:
128K x 36 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
64 independent 2K x 36 banks
– 4 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A10L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2015 Integrated Device Technology, Inc.
MUX
2Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 1)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
1
TMS
TCK
TRST
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A10R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5626 drw 01
,
JUNE 2015
DSC 5626/7



No Preview Available !

IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
2Kx36 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 2Kx36 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
register, the IDT70V7599 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE0 and CE1, permits the on-chip circuitry of each
port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.
The 70V7599 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(VDD) remains at 3.3V. Please refer also to the
functional description on page 19.
Pin Configuration(1,2,3,4)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10 A11 A12
A13 A14 A15 A16 A17
IO19L IO18L VSS TDO NC BA5L BA1L A8L BE1L VDD CLKL CNTENL A4L A0L OPTL I/O17L VSS
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
I/O20R VSS I/O18R TDI NC BA2L A9L BE2L CE0L VSS ADSL A5L A1L VSS VDDQR I/O16L I/O15R
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
VDDQL I/O19R VDDQR PL/FTL NC BA3L A10L BE3L CE1L VSS R/WL A6L A2L VDD I/O16R I/O15L VSS
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
I/O22L VSS I/O21L I/O20L BA4L BA0L A7L BE0L VDD OEL REPEATL A3L VDD I/O17R VDDQL I/O14L I/O14R
E1 E2 E3 E4
I/O23L I/O22R VDDQR I/O21R
E14 E15 E16 E17
I/O12L I/O13R VSS I/O13L
F1 F2 F3 F4
VDDQL I/O23R I/O24L VSS
F14 F15 F16 F17
VSS I/O12R I/O11L VDDQR
G1 G2 G3 G4
I/O26L VSS I/O25L I/O24R
G14 G15 G16 G17
I/O9L VDDQL I/O10L I/O11R
H1 H2 H3 H4
VDD I/O26R VDDQR I/O25R
J1 J2 J3 J4
VDDQL VDD VSS VSS
K1 K2 K3 K4
I/O28R VSS I/O27R VSS
70V7599BF
BF208(5)
208-Pin fpBGA
Top View(6)
H14 H15 H16 H17
VDD IO9R VSS I/O10R
J14 J15 J16 J17
VSS VDD VSS VDDQR
K14 K15 K16 K17
I/O7R VDDQL I/O8R VSS
L1 L2 L3 L4
I/O29R I/O28L VDDQR I/O27L
L14 L15 L16 L17
I/O6R I/O7L VSS I/O8L
M1 M2 M3 M4
VDDQL I/O29L I/O30R VSS
M14 M15 M16 M17
VSS I/O6L I/O5R VDDQR
N1 N2 N3 N4
I/O31L VSS I/O31R I/O30L
N14 N15 N16 N17
I/O3R VDDQL I/O4R I/O5L
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17
I/O32R I/O32L VDDQR I/O35R TRST BA5R BA1R A8R BE1R VDD CLKR CNTENR A4R I/O2L I/O3L VSS I/O4L
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
VSS I/O33L I/O34R TCK NC BA2R A9R BE2R CE0R VSS ADSR A5R A1R VSS VDDQL I/O1R VDDQR
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
I/O33R I/O34L VDDQL TMS NC BA3R A10R BE3R CE1R VSS R/WR A6R A2R VSS I/O0R VSS I/O2R
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10
VSS I/O35L PL/FTR NC BA4R BA0R A7R BE0R VDD OER
U12 U13 U14 U15 U16 U17
A3R A0R VDD OPTR I/O0L I/O1L
NOTES:
5626 drw 02c
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.422



No Preview Available !

IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Configuration(1,2,3,4) (con't.)
Industrial and Commercial Temperature Ranges
70V7599BC
BC256(5)
A1 A2
A3 A4
NC TDI NC NC
256-Pin BGA
Top View(6)
A5
A6 A7
A8 A9
A10 A11 A12
A13 A14 A15 A16
BA3L BA0L A8L BE2L CE1L OEL CNTENL A5L A2L A0L NC NC
B1
B2
B3
B4
B5 B6
B7
B8 B9
B10 B11
B12 B13 B14 B15 B16
I/O18L NC TDO NC BA4L BA1L A9L BE3L CE0L R/WL REPEATL A4L A1L VDD I/O17L NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
I/O18R I/O19L VSS BA5L BA2L A10L A7L BE1L BE0L CLKL ADSL A6L A3L OPTL I/O17R I/O16L
D1 D2 D3 D4
D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15 D16
I/O20R I/O19R I/O20L PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
E5
E6 E7
E8
E9
E10 E11
E12 E13
E14 E15 E16
I/O21R I/O21L I/O22L VDDQL VDD VDD VSS VSS VSS VSS VDD VDD VDDQR I/O13L I/O14L I/O14R
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
I/O23L I/O22R I/O23R VDDQL VDD VSS VSS VSS VSS VSS VSS VDD VDDQR I/O12R I/O13R I/O12L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
I/O24R I/O24L I/O25L VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O10L I/O11L I/O11R
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
I/O26L I/O25R I/O26R VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O9R IO9L I/O10R
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16
I/O27L I/O28R I/O27R VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR I/O8R I/O7R I/O8L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16
I/O29R I/O29L I/O28L VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR I/O6R I/O6L I/O7L
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16
I/O30L I/O31R I/O30R VDDQR VDD VSS VSS VSS VSS VSS VSS VDD VDDQL I/O5L I/O4R I/O5R
M1 M2 M3 M4
M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
I/O32R I/O32L I/O31L VDDQR VDD VDD VSS VSS VSS VSS VDD VDD VDDQL I/O3R I/O3L I/O4L
N1 N2 N3 N4
N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
I/O33L I/O34R I/O33R PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD I/O2L I/O1R I/O2R
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
I/O35R I/O34L TMS BA5R BA2R A10R A7R BE1R BE0R CLKR ADSR A6R A3R I/O0L I/O0R I/O1L
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
I/O35L NC TRST NC BA4R BA1R A9R BE3R CE0R R/WR REPEATR A4R A1R OPTR NC NC
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
NC TCK NC NC BA3R BA0R A8R BE2R CE1R OER CNTENR A5R A2R A0R NC NC
NOTES:
5626 drw 02d
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.432



No Preview Available !

IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Configuration(1,2,3,4) (con't.)
Industrial and Commercial Temperature Ranges
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V7599DR
DR208(5)
208-Pin PQFP
Top View(6)
156 I/O16L
155 I/O16R
154 I/O15L
153 I/O15R
152 VSS
151 VDDQL
150 I/O14L
149 I/O14R
148 I/O13L
147 I/O13R
146 VSS
145 VDDQR
144 I/O12L
143 I/O12R
142 I/O11L
141 I/O11R
140 VSS
139 VDDQL
138 I/O10L
137 I/O10R
136 I/O9L
135 I/O9R
134 VSS
133 VDDQR
132 VDD
131 VDD
130 VSS
129 VSS
128 VSS
127 VDDQL
126 I/O8R
125 I/O8L
124 I/O7R
123 I/O7L
122 VSS
121 VDDQR
120 I/O6R
119 I/O6L
118 I/O5R
117 I/O5L
116 VSS
115 VDDQL
114 I/O4R
113 I/O4L
112 I/O3R
111 I/O3L
110 VSS
109 VDDQR
108 I/O2R
107 I/O2L
106 I/O1R
105 I/O1L
5626 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.442




IDT70V7599S datasheet pdf
Download PDF
IDT70V7599S pdf
View PDF for Mobile


Similiar Datasheets : IDT70V7599S

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Privacy Policy + Contact