IDT70V7339S Datasheet PDF - IDT


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IDT70V7339S
IDT

Part Number IDT70V7339S
Description HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
Page 22 Pages

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HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
IDT70V7339S
Features:
512K x 18 Synchronous Bank-Switchable Dual-ported SRAM
Architecture
64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus match-
ing compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on each
port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
I/O0L-17L
I/O
CONTROL
A12L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. TheBank-Switchabledual-portusesatrueSRAMcore
instead of the traditional dual-port SRAM core. As a result, it
has unique operating characteristics. Please refer to the
functionaldescriptiononpage18fordetails.
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
TMS
TCK
TRST
©2015 Integrated Device Technology, Inc.
1
CONTROL
LOGIC
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O
CONTROL
I/O0R-17R
ADDRESS
DECODE
BANK
DECODE
A12R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5628 drw 01
,
AUGUST 2015
DSC 5628/10



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IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 8Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
register, the IDT70V7339 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power
down feature, controlled by CE0 andCE1, permits the on-chip circuitry of
each porttoenteraverylowstandbypowermode.Thedualchipenables
also facilitate depth expansion.
The 70V7339 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(VDD) remains at 3.3V. Please refer also to the
functional description on page 18.
Pin Configuration(1,2,3,4)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10 A11 A12
A13 A14 A15 A16 A17
IO9L NC VSS TDO NC BA3L A12L A8L NC VDD CLKL CNTENL A4L A0L OPTL NC VSS
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
NC VSS NC TDI BA4L BA0L A9L NC CE0L VSS ADSL A5L A1L VSS VDDQR I/O8L NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
VDDQL I/O9R VDDQR PL/FTL BA5L BA1L A10L UBL CE1L VSS R/WL A6L A2L VDD I/O8R NC VSS
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
NC VSS I/O10L NC BA2L A11L A7L LBL VDD OEL REPEATL A3L VDD NC VDDQL I/O7L I/O7R
E1 E2 E3 E4
I/O11L NC VDDQR I/O10R
E14 E15 E16 E17
I/O6L NC VSS NC
F1 F2 F3 F4
VDDQL I/O11R NC VSS
F14 F15 F16 F17
VSS I/O6R NC VDDQR
G1 G2 G3 G4
NC VSS I/O12L NC
G14 G15 G16 G17
NC VDDQL I/O5L NC
H1 H2 H3 H4
VDD NC VDDQR I/O12R
J1 J2 J3 J4
VDDQL VDD VSS VSS
K1 K2 K3 K4
I/O14R VSS I/O13R VSS
70V7339BF
BF-208(5)
208-Pin fpBGA
Top View(6)
H14 H15 H16 H17
VDD NC VSS I/O5R
J14 J15 J16 J17
VSS VDD VSS VDDQR
K14 K15 K16 K17
I/O3R VDDQL I/O4R VSS
L1 L2 L3 L4
NC I/O14L VDDQR I/O13L
L14 L15 L16 L17
NC I/O3L VSS I/O4L
M1 M2 M3 M4
VDDQL NC I/O15R VSS
M14 M15 M16 M17
VSS NC I/O2R VDDQR
N1 N2 N3 N4
NC VSS NC I/O15L
N14 N15 N16 N17
I/O1R VDDQL NC I/O2L
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17
I/O16R I/O16L VDDQR NC TRST BA3R A12R A8R NC VDD CLKR CNTENR A4R NC I/O1L VSS NC
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
VSS NC I/O17R TCK BA4R BA0R A9R NC CE0R VSS ADSR A5R A1R VSS VDDQL I/O0R VDDQR
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
NC I/O17L VDDQL TMS BA5R BA1R A10R UBR CE1R VSS R/WR A6R A2R VSS NC VSS NC
U1 U2 U3
U4 U5
U6 U7 U8
U9 U10 U11 U12 U13 U14 U15 U16 U17
VSS NC PL/FTR NC BA2R A11R A7R LBR VDD OER REPEATR A3R A0R VDD OPTR NC I/O0L
NOTES:
1. AllVDD pinsmustbeconnectedto3.3Vpowersupply.
2. AllVDDQ pinsmustbeconnectedtoappropriatepowersupply:3.3VifOPTpinforthatportissettoVIH(3.3V),and2.5VifOPTpinforthatportis
settoVIL (0V).
3. AllVSSpinsmustbeconnectedtogroundsupply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. Thispackagecodeisusedtoreferencethepackagediagram.
6. Thistextdoesnotindicateorientationoftheactualpart-marking.
6.422
5628 drw 02c



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IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Configuration(1,2,3,4) (con't.)
Industrial and Commercial Temperature Ranges
70V7339BC
BC-256(5)
256-Pin BGA
Top View(6)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10 A11 A12
A13 A14 A15 A16
NC TDI NC BA4L BA1L A11L A8L NC CE1L OEL CNTENL A5L A2L A0L NC NC
B1
B2 B3
B4
B5 B6
B7
B8 B9
B10 B11
B12 B13 B14 B15 B16
NC NC TDO BA5L BA2L A12L A9L UBL CE0L R/WL REPEATL A4L A1L VDD NC NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
NC I/O9L VSS BA3L BA0L A10L A7L NC LBL CLKL ADSL A6L A3L OPTL NC I/O8L
D1 D2 D3 D4
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
NC I/O9R NC PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD NC NC I/O8R
E1
E2
E3
E4
E5 E6 E7
E8
E9
E10 E11
E12 E13
E14 E15
E16
I/O10R I/O10L NC VDDQL VDD VDD VSS VSS VSS VSS VDD VDD VDDQR NC I/O7L I/O7R
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
I/O11L NC I/O11R VDDQL VDD VSS VSS VSS VSS VSS VSS VDD VDDQR I/O6R NC I/O6L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
NC NC I/O12L VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O5L NC NC
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
NC I/O12R NC VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL NC NC I/O5R
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16
I/O13L I/O14R I/O13R VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR I/O4R I/O3R I/O4L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16
NC NC I/O14L VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR NC NC I/O3L
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16
I/O15L NC I/O15R VDDQR VDD VSS VSS VSS VSS VSS VSS VDD VDDQL I/O2L NC I/O2R
M1 M2 M3 M4
M5 M6
M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
I/O16R I/O16L NC VDDQR VDD VDD VSS VSS VSS VSS VDD VDD VDDQL I/O1R I/O1L NC
N1 N2 N3 N4
N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
NC I/O17R NC PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD NC I/O0R NC
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
NC I/O17L TMS BA3R BA0R A10R A7R NC LBR CLKR ADSR A6R A3R NC NC I/O0L
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
NC NC TRST BA5R BA2R A12R A9R UBR CE0R R/WR REPEATR A4R A1R OPTR NC NC
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
NC TCK NC BA4R BA1R A11R A8R NC CE1R OER CNTENR A5R A2R A0R NC NC
NOTES:
1. AllVDD pinsmustbeconnectedto3.3Vpowersupply.
2. AllVDDQpinsmustbeconnectedtoappropriatepowersupply:3.3VifOPTpinforthatportissettoVIH (3.3V),and2.5VifOPTpinforthatportis
settoVIL (0V).
3. AllVSSpinsmustbeconnectedtogroundsupply.
4. Packagebodyisapproximately17mmx17mmx1.4mm,with1.0mmball-pitch.
5. Thispackagecodeisusedtoreferencethepackagediagram.
6. Thistextdoesnotindicateorientationoftheactualpart-marking.
5628 drw 02d
6.432



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IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
Chip Enables
Read/Write Enable
OEL
BA0L - BA5L
OER
BA0R - BA5R
Output Enable
Bank Address(4)
A0L - A12L
A0R - A12R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL CLKR Clock
PL/FTL
PL/FTR
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
REPEATL
LBL, UBL
VDDQL
OPTL
CNTENR
REPEATR
LBR, UBR
VDDQR
OPTR
VDD
VSS
TDI
TDO
TCK
TMS
Counter Enable
Counter Repeat(3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
Option for selecting VDDQX(1,2)
Power (3.3V)(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
NOTES:
1. VDD,OPTX,andVDDQXmustbesettoappropriateoperatinglevelspriortoapplyinginputs
on the I/Os and controls for that port.
2. OPTXselectstheoperatingvoltagelevelsfortheI/Osandcontrolsonthatport.IfOPTXis
settoVIH(3.3V),thenthatport'sI/Osandcontrolswilloperateat3.3VlevelsandVDDQXmust
be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and address controls will
operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent
ofoneanother—bothportscanoperateat3.3Vlevels,bothcanoperateat2.5Vlevels,oreither
can operate at 3.3V with the other at 2.5V.
3. WhenREPEATXisasserted,thecounterwillresettothelastvalidaddressloadedviaADSX.
4. Accessesbytheportsintospecificbanksarecontrolledbythebankaddresspinsunder
the user's direct control: each port can access any bank of memory with the shared array
thatisnotcurrentlybeingaccessedbytheoppositeport(i.e.,BA0L -BA5LBA0R-BA5R).
In the event that both ports try to access the same bank at the same time, neither access
willbevalid,anddataatthetwospecificaddressestargetedbytheportswithinthatbankmay
be corrupted (in the case that either or both ports are writing) or may result in invalid output
(in the case that both ports are trying to read).
TRST
Reset (Initialize TAP Controller)
5628 tbl 01
6.442




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