IDT70T3799 Datasheet PDF - IDT


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IDT70T3799
IDT

Part Number IDT70T3799
Description HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM
Page 25 Pages

IDT70T3799 datasheet pdf
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HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
IDT70T3719/99M
Š DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
Green parts available, see ordering information
Functional Block Diagram
BE7L
BE7R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0h 1h
h
1h 0h
h
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
FT/PIPEL
1
0
1/0
1h 0h
0/1
a
1a 0a
h
Byte 0
I/O0L - I/O71L
CLKL
A17L(1)
A 0L
REPEATL
ADSL
CN TENL
Byte 7
Counter/
Address
Reg.
B
BB
B
W
WW
W
0
77
0
L
LR
R
D OUT0-8_ L
D OUT9-17 _L
DO UT18-26_L
D OUT 27-3 5_ L
D OUT 36-4 4_L
D OUT 45-5 3_L
D OUT 54-6 2_L
D OUT 63-7 2_L
D OUT0-8_ R
D OUT9-17 _R
D OU T1 8-2 6_ R
DOUT27 -35_ R
DOUT36 -4 4_ R
DOUT45 -5 3_ R
DOUT54 -6 2_ R
DOUT63 -7 2_ R
256/128K x 72
MEM ORY
ARRAY
DIN_L
DIN_R
ADDR_L
ADDR_R
0a 1a
h
0h 1h
a
0/1
Byte 7
Counter/
Address
Reg.
Byte 0
I/O0R - I/O71R
A17R(1)
CLKR
A 0R
REPE ATR
AD SR
CNTENR
COL L
INTL
CE0L
CE1L
R/WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0R
CE1R
R/WR
COL R
INTR
NOTES:
ZZ
(2)
L
ZZ
CONTROL
LOGIC
ZZ
(2)
R
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2014 Integrated Device Technology, Inc.
TDI
T DO
C E0 R
1 CE1R
0
1/0
OER
FT/PIPER
,
,
JTAG
TC K
TMS
TRST
5687 drw 01
JULY 2014
DSC 5687/3



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IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro-
nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3719/99M has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3719/99M can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.422



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IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4,5)
70T3719/99M
BBG-324(6)
324-Pin BGA
Top View(7)
06/27/05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
A I/O39R I/O38R I/O37R I/O36R COLL A15L A12L A8L BE7L BE2L CE1L ADSL A6L A1L I/O32R I/O33R I/O34R I/O35R A
B I/O39L I/O38L I/O37L I/O36L TDO A17L(1) A13L A10L BE6L BE5L BE1L OEL REPEATL A0L I/O32L I/O33L I/O34L I/O35L B
C I/O40R I/O41R I/O42R I/O43R INTL A16L A11L A7L BE0L CE0L R/WL CNTENL A4L A3L I/O31R I/O30R I/O29R I/O28R C
D I/O40L I/O41L I/O42L I/O43L TDI NC A14L A9L BE4L BE3L CLKL A5L A2L ZZL I/O31L I/O30L I/O29L I/O28L D
E I/O47R I/O46R I/O45R I/O44R PL/FTL VDD VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR OPTL I/O24R I/O25R I/O26R I/O27R E
F I/O47L I/O46L I/O45L I/O44L VDD VDD VDDQL Vss Vss Vss VDD VDD VDD VDD I/O24L I/O25L I/O26L I/O27L F
G I/O48R I/O49R I/O50R I/O51R VDDQR VDDQR Vss Vss Vss Vss Vss Vss VDDQR VDDQR I/O23R I/O22R I/O21R I/O20R G
H I/O48L I/O49L I/O50L I/O51L VDDQL VDDQL Vss Vss Vss Vss Vss Vss VDDQL VDDQL I/O23L I/O22L I/O21L I/O20L H
J I/O55R I/O54R I/O53R I/O52R VDDQR Vss Vss Vss Vss Vss Vss Vss Vss VDDQR I/O16R I/O17R I/O18R I/O19R J
K I/O55L I/O54L I/O53L I/O52L VDDQR Vss Vss Vss Vss Vss Vss Vss Vss VDDQR I/O16L I/O17L I/O18L I/O19L K
L I/O56R I/O57R I/O58R I/O59R VDDQL Vss Vss Vss Vss Vss Vss Vss Vss VDDQL I/O15R I/O14R I/O13R I/O12R L
M I/O56L I/O57L I/O58L I/O59L VDDQL VDD Vss Vss Vss Vss Vss Vss VDDQL VDDQL I/O15L I/O14L I/O13L I/O12L M
N I/O63R I/O62R I/O61R I/O60R VDDQR VDDQR VDDQL VDDQL Vss Vss VDD VDDQR VDDQR VDDQR I/O8R I/O9R I/O10R I/O11R N
P I/O63L I/O62L I/O61L I/O60L ZZR TMS VDD VDD VDD VDDQL VDDQL VDD VDD OPTR I/O8L I/O9L I/O10L I/O11L P
R I/O64R I/O65R I/O66R I/O67R COLR A17R(1) A12R A9R BE4R CE0R OER A6R A2R A1R I/O7R I/O6R I/O5R I/O4R R
T I/O64L I/O65L I/O66L I/O67L PL/FTR A16R A13R A7R BE7R BE3R CE1R ADSR A4R A0R I/O7L I/O6L I/O5L I/O4L T
U I/O71R I/O70R I/O69R I/O68R TCK INTR A14R A10R BE2R BE6R BE1R R/WR REPEATR A3R I/O0R I/O1R I/O2R I/O3R U
V I/O71L I/O70L I/O69L I/O68L TRST NC A15R A11R A8R BE5R BE0R CLKR CNTENR A5R I/O0L I/O1L I/O2L I/O3L V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
5687 tbl 01
NOTES:
1. Pin is a NC for IDT70T3799.
2. All VDD pins must be connected to 2.5V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 19mm x 19mm x 1.76mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.432



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IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A17L(5)
OER
A0R - A17R(5)
I/O0L - I/O71L
I/O0R - I/O71R
CLKL
CLKR
PL/FTL
PL/FTR
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
BE0L - BE7L
VDDQL
OPTL
BE0R - BE7R
VDDQR
OPTR
ZZL ZZR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
INTL
COLL
INTR
COLR
Names
Chip Enables (Input)(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
Byte Enables (9-bit bytes) (Input)(6)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
5687 tbl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A17x is a NC for the IDT70T3799M.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.442




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