IDT70T3339S Datasheet PDF - IDT


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IDT70T3339S
IDT

Part Number IDT70T3339S
Description HIGH-SPEED 2.5V 512/256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM
Page 27 Pages

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HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UBL
LBL
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
ab
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Dout9-17_R
1b 0b
b
1a 0a
a
1/0
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
512/256/128K x 18
MEMORY
ARRAY
0a 1a 0b
1b
ba
0/1
FT/PIPER
,
I/O0L - I/O17L
Din_L
Din_R
I/O0R - I/O17R
CLKL
A18L(1)
A0L
REPEATL
ADSL
CNTENL
COL L
INTL
Counter/
Address
Reg.
CE 0 L
CE 1L
R/W L
ADDR_L
ADDR_R
INTERRUPT
COLLISION
DETECTION
LOGIC
ZZL(2)
ZZ
CO NTRO L
LOGIC
Counter/
Address
Reg.
R/WR
CE0 R
CE1R
ZZR(2)
CLKR
A18R(1)
A0R
REPEATR
ADSR
CNTENR
TDI
TDO
COLR
INTR
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2015 Integrated Device Technology, Inc.
1
,
TCK
JTAG TMS
TRST
5652 drw 01
JUNE 2015
DSC-5652/8



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IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70T3339/19/99 has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70T3339/19/99 can support an operating voltage of either
3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.422



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IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Pin Configuration (3,4,5,6,9)
Industrial and Commercial Temperature Ranges
70T3339/19/99BC
BC-256(8)
256-Pin BGA
Top View(9)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10 A11 A12 A13 A14 A15 A16
NC TDI NC A17L(2) A14L A11L A8L NC CE1L OEL CNTENL A5L A2L A0L NC NC
B1
B2 B3
B4
B5 B6
B7
B8 B9
B10 B11
B12 B13 B14 B15 B16
INTL NC TDO A18L(1) A15L A12L A9L UBL CE0L R/WL REPEATL A4L A1L VDD NC NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
COLL I/O9L VSS A16L A13L A10L A7L NC LBL CLKL ADSL A6L A3L OPTL NC I/O8L
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
NC I/O9R NC PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD NC NC I/O8R
E1
E2
E3
E4
E5
E6 E7
E8
E9
E10 E11
E12 E13
E14 E15
E16
I/O10R I/O10L NC VDDQL VDD VDD NC VSS VSS VSS VDD VDD VDDQR NC I/O7L I/O7R
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
I/O11L NC I/O11R VDDQL VDD NC NC VSS VSS VSS VSS VDD VDDQR I/O6R NC I/O6L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
NC NC I/O12L VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O5L NC NC
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
NC I/O12R NC VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL NC NC I/O5R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10 J11
J12 J13
J14 J15
J16
I/O13L I/O14R I/O13R VDDQL ZZR VSS VSS VSS VSS VSS VSS ZZL VDDQR I/O4R I/O3R I/O4L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16
NC NC I/O14L VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR NC NC I/O3L
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16
I/O15L NC I/O15R VDDQR VDD NC NC VSS VSS VSS VSS VDD VDDQL I/O2L NC I/O2R
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
I/O16R I/O16L NC VDDQR VDD VDD NC VSS VSS VSS VDD VDD VDDQL I/O1R I/O1L NC
N1 N2 N3 N4
N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
NC I/O17R NC PIPE/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD NC I/O0R NC
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
COLR I/O17L TMS A16R A13R A10R A7R NC LBR CLKR ADSR A6R A3R NC NC I/O0L
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
INTR NC TRST A18R(1) A15R A12R A9R UBR CE0R R/WR REPEATR A4R A1R OPTR NC NC
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
NC TCK NC A17R(2) A14R A11R A8R NC CE1R OER CNTENR A5R A2R A0R NC NC
NOTES:
5652 drw 02d
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.
6.342



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IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Pin Configurations(con't)(3,4,5,6,9)
Industrial and Commercial Temperature Ranges
12 3 4 56 7 8
I/O9L INTL VSS TDO NC A16L
A12L A8L
9 10 11 12 13 14 15 16 17
NC VDD CLKL CNTEN L A4L
A0L OPT L NC VSS
A
BNC VSS COLL TDI A17L(2) A13L A9L NC CE0L VSS ADSL A5L A1L NC VDDQR I/O8L NC
VDDQL I/O9R VDDQR PIPE/FTL A18L(1) A14L A10L
UBL CE1L
VSS R/WL
A6L
CA2L VDD I/O8R NC VSS
DNC
VSS I/O10L NC
A15L A11L
A7L
LBL VDD OEL REPEATL A3L VDD
NC VDDQL I/O7L I/O7R
I/O11L NC VDDQR I/O10R
I/O6L NC
VSS NC
E
VDDQL I/O11R NC
VSS
FVSS I/O6R NC VDDQR
NC VSS I/O12L NC
GNC VDDQL I/O5L NC
VDD NC VDDQR I/O12R
VDDQL VDD VSS ZZR
I/O14R VSS I/O13R VSS
NC I/O14L VDDQR I/O13L
70T3339/19/99BF
BF-208(7)
208-Pin fpBGA
Top View(8)
HVDD NC
VSS I/O5R
JZZL VDD VSS VDDQR
I/O3R VDDQL I/O4R VSS
K
LNC I/O3L VSS I/O4L
VDDQL NC I/O15R VSS
MVSS NC I/O2R VDDQR
NC VSS NC I/O15L
NI/O1R VDDQL NC I/O2L
I/O16R I/O16L VDDQR COLR TRST A16R A12R A8R NC
VDD CLKR CNTEN R A4R NC
I/O1L VSS
NC P
RVSS NC I/O17R TCK A17R(2) A13R A9R NC CE0R VSS ADSR A5R A1R NC VDDQL I/O0R VDDQR
TNC I/O17L VDDQL TMS A18R(1) A14R A10R UBR CE1R VSS R/WR A6R A2R VSS NC VSS NC
UVSS INTR PIPE/FTR NC
A15R A11R
A7R
LBR
VDD
OER REPEATR A3R
A0R
VDD OPT R NC I/O0L
5652 drw 02c
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
6.42




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