IDT709159 Datasheet PDF - IDT


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IDT709159
IDT

Part Number IDT709159
Description HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Page 16 Pages

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HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709169/59L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
Low-power operation
– IDT709169/59L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time,100MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
NOTE:
1. A13 is a NC for IDT709159.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5653 drw 01
©2009 Integrated Device Technology, Inc.
1
JANUARY 2009
DSC-5653/3



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IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT709169/59 is a high-speed 16/8K x 9 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709169/59 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 925mW of power.
Pin Configurations(1,2,3,4)
06/28/02
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L(1)
NC
NC
NC
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1 100 99 98 97
96 95
94
93 92
91 90
89 88
87 86
85 84
83 82
81
80 79
78 77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9
709169/59PF
67
10 PN100-1(5) 66
11 65
12 100-Pin TQFP 64
13 Top View(6) 63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R(1)
NC
NC
NC
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
5653 drw 02
.
NOTES:
1. A13 is a NC for IDT709159.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.242



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IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)(1,2,3,4)
709169/59BF
BF100(5)
06/28/02
100-Pin fpBGA
Top View(6)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10
A6R A9R A12R NC GND GND NC R/WR GND NC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
A4R A5R A8R A10R NC NC NC OER NC I/O6R
C1 C2 C3 C4 C5 C6 C7 C8
C9 C10
A3R NC NC A7R NC CE0R CE1R PL/FTR I/O7R I/O3R
D1 D2 D3 D4 D5 D6 D7
D8 D9 D10
A0R CLKR A1R A2R A11R A13R(1) CNTRSTR I/O8R I/O5R I/O1R
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
GND ADSR CNTENR A1L ADSL GND I/O4R I/O2R I/O0R VCC
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
GND CLKL A0L A3L VCC GND VCC I/O2L I/O1L I/O0L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
CNTENL NC A5L A12L NC R/WL NC I/O4L GND I/O3L
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
A2L A4L A9L A13L(1) NC CE1L NC I/O7L I/O6L I/O5L
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
NC A7L A10L NC NC NC OEL GND GND I/O8L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
A6L A8L A11L NC VCC VCC CE0L CNTRSTL PL/FTL NC
,
NOTES:
1. A13 is a NC for IDT709159.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
5653 drw 03
6.342



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IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
CE0L, CE1L
R/WL
OEL
A0L - A13L(1)
I/O0L - I/O8L
CLKL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
Right Port
CE0R, CE1R
R/WR
OER
A0R - A13R(1)
I/O0R - I/O8R
CLKR
ADSR
CNTENR
CNTRSTR
FT/PIPER
VCC
GND
NOTE:
1. A13 is a NC for IDT709159.
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
Ground (0V)
5653 tbl 01
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-8
Mode
XHXX
High-Z Deselected—Power Down
XX LX
High-Z Deselected—Power Down
XL HL
DATAIN Write
L L H H DATAOUT Read
HX L HX
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
5653 tbl 02
6.442




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