IDT709099L Datasheet PDF - IDT


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IDT709099L
IDT

Part Number IDT709099L
Description HIGH-SPEED 128K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Page 16 Pages

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HIGH-SPEED 128K x 8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709099L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT709099L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66.7MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O7R
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4846 drw 01
©2015 Integrated Device Technology, Inc.
1
APRIL 2015
DSC-4846/8



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IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT709099 is a high-speed 128K x 8 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709099 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devices typically operate on only 1.2W of power.
Pin Configurations(1,2,3)
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1100 99 98 97
96 95
94 93
92 91 90
89 88
87 86
85 84
83 82 81
80 79
78 77 76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 IDT709099PF 66
11 PN100(4) 65
12 64
13 100-PIN TQFP 63
14 TOP VIEW(5) 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
.
4846 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.242



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IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
OEL
A0L - A16L
I/O0L - I/O7L
CLKL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
CE0R, CE1R
R/WR
OER
A0R - A16R
I/O0R - I/O7R
CLKR
ADSR
CNTENR
CNTRSTR
FT/PIPER
VCC
GND
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
4846 tbl 01
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-7
X HX X
High-Z
Deselected—Power Down
XX LX
High-Z
Deselected—Power Down
XL HL
DATAIN
Write
LL HH
DATAOUT
Read
HX L HX
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Mode
4846 tbl 02
Truth Table II—Address Counter Control(1,2,6)
Previous
Address Address
Addr
Used
CLK ADS CNTEN CNTRST
I/O(3)
Mode
XX
0
X
X
L
DI/O(0) Counter Reset to Address 0
An X An L(4) X H DI/O(n) External Address Utilized
An Ap Ap H H H DI/O(n) External Address Blocked—Counter Disabled (Ap reused)
X
Ap
Ap + 1
H
L(5) H
DI/O(n+1) Counter Enable—Internal Address Generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
4846 tbl 03
6.342



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IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(2)
GND
Vcc
Commercial
0OC to +70OC
0V
5.0V + 10%
Industrial
-40OC to +85OC
0V
5.0V + 10%
NOTES:
4846 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
VIH Input High Voltage
2.2 ____ 6.0(1) V
VIL Input Low Voltage
-0.5(2)
____
0.8
V
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
4846 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS Temperature
Under Bias
-55 to +125
oC
TSTG Storage
Temperature
-65 to +150
oC
IOUT DC Output
Current
50 mA
NOTES:
4846 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT(3) Output Capacitance
VOUT = 3dV
10 pF
NOTES:
4846 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
Symbol
|ILI|
|ILO|
VOL
VOH
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC
IOL = +4mA
IOH = -4mA
709099L
Min. Max.
___ 5
___ 5
___ 0.4
2.4 ___
Unit
µA
µA
V
V
4846 tbl 08
6.442




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