IDT709079S Datasheet PDF - IDT


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IDT709079S
IDT

Part Number IDT709079S
Description HIGH-SPEED 32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
Page 17 Pages

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HIGH-SPEED 32K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
PRELIMINARY
IDT709079S/L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT709079S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709079L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPER pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
OEL
R/WR
OER
CE0L
CE1L
1
0
0/1
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
I/O0R - I/O7R
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3495 drw 01
DECEMBER 2002
©2002 Integrated Device Technology, Inc.
1
DSC 3495/8



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IDT709079S/L
High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description:
The IDT709079 is a high-speed 32K x 8 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
With an input data register, the IDT709079 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 950mW of power.
Pin Configurations(1,2,3)
03/18/02
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1 100 99 98
97 96
95 94
93 92
91
90 89 88 87 86
85 84
83 82
81
80 79
78 77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 IDT709079PF
11 PN100-1(4)
66
65
12
13 100-PIN TQFP
14 TOP VIEW(5)
64
63
62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
,
3495 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.422



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IDT709079S/L
High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
OEL
A0L - A14L
I/O0L - I/O7L
CLKL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
CE0R, CE1R
R/WR
OER
A0R - A14R
I/O0R - I/O7R
CLKR
ADSR
CNTENR
CNTRSTR
FT/PIPER
VCC
GND
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
3495 tbl 01
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and En-
able Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-7
Mode
X H X X High-Z Deselected
X X L X High-Z Deselected
XLH L
DIN Write
LLH H
DOUT Read
HX L H X
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
3495 tbl 02
Truth Table II—Address Counter Control(1,2)
Previous Addr
Address Address Used CLK ADS CNTEN CNTRST
I/O(3)
MODE
X X 0 X X L(4) DI/O(0) Counter Reset to Address 0
An
X An L(4) X
H DI/O (n) External Address Used
An Ap Ap H H H DI/O(p) External Address Blocked—Counter disabled (Ap reused)
X
Ap Ap + 1 H L(5)
H DI/O(p+1) Counter Enabled—Internal Address generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
3495 tbl 03
6.432



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IDT709079S/L
High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature(1)
GND
Vcc
Commercial
0OC to +70OC
0V
5.0V + 10%
Industrial
-40OC to +85OC
0V
5.0V + 10%
NOTES:
3495 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
VIH Input High Voltage
2.2 ____ 6.0(1) V
VIL Input Low Voltage
-0.5(2)
____
0.8
V
NOTES:
1. VTERM must not exceed VCC +10%.
2. VIL > -1.5V for pulse width less than 10ns.
3495 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS Temperature
Under Bias
-55 to +125
oC
TSTG Storage
Temperature
-65 to +150
oC
IOUT DC Output
Current
50 mA
NOTES:
3495 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliabil-
ity.
2. VTERM must not exceed Vcc +10% for more than 25% of the cycle
time or 10ns maximum, and is limited to < 20mA for the period of
VTERM > Vcc + 10%.
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT(3) Output Capacitance
VOUT = 3dV
10 pF
NOTES:
3495 tbl 07
1. These parameters are determined by device characterization, but are not pro-
duction tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
6.442




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