ICS9UMS9633BI Datasheet PDF - IDT

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ICS9UMS9633BI
IDT

Part Number ICS9UMS9633BI
Description ULTRA MOBILE PC CLOCK
Page 22 Pages


ICS9UMS9633BI datasheet pdf
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Advance Information
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL
TEMPERATURE RANGE
ICS9UMS9633BI
Recommended Application:
Poulsbo Based Ultra-Mobile PC (UMPC) for Industrial
Temperature Range
Output Features:
• 3 - CPU low power differential push-pull pairs
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
Features/Benefits:
• Industrial temperature range compliant
• Supports ULV CPUs with 67 to 167 MHz
CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO operation, 3.3V VDD core and
REF supply pin for REF
• -40 to +85C operating range
SSOP Pin Configuration
REF 1
GNDREF 2
VDDCORE_3.3 3
FSC_L 4
TEST_MODE 5
TEST_SEL 6
SCLK 7
SDATA 8
VDDCORE_3.3 9
VDDIO_1.5 10
DOT96C_LPR 11
DOT96T_LPR 12
GNDDOT 13
GNDLCD 14
LCD100C_LPR 15
LCD100T_LPR 16
VDDIO_1.5 17
VDDCORE_3.3 18
*CR#0 19
GNDSRC 20
SRCC0_LPR 21
SRCT0_LPR 22
*CR#1 23
VDDCORE_3.3 24
48 VDDREF_3.3
47 X1
46 X2
45 CLKPWRGD#/PD_3.3
44 CPU_STOP#
43 CPUT0_LPR
42 CPUC0_LPR
41 VDDIO_1.5
40 GNDCPU
39 CPUT1_LPR
38 CPUC1_LPR
37 VDDCORE_3.3
36 VDDIO_1.5
35 GNDCPU
34 CPUT2_LPR
33 CPUC2_LPR
32 FSB_L
31 *CR#2
30 SRCT2_LPR
29 SRCC2_LPR
28 GNDSRC
27 SRCT1_LPR
26 SRCC1_LPR
25 VDDIO_1.5
48 SSOP Package
* indicates inputs with internal pull up of ~10Kohm to 3.3V
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
1
1451—01/20/09
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ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
Advance Information
SSOP Pin Description
PIN #
PIN NAME
1 REF
2 GNDREF
3 VDDCORE_3.3
4 FSC_L
5 TEST_MODE
6 TEST_SEL
7 SCLK
8 SDATA
9 VDDCORE_3.3
10 VDDIO_1.5
11 DOT96C_LPR
12 DOT96T_LPR
13 GNDDOT
14 GNDLCD
15 LCD100C_LPR
16 LCD100T_LPR
17 VDDIO_1.5
18 VDDCORE_3.3
19 *CR#0
20 GNDSRC
21 SRCC0_LPR
22 SRCT0_LPR
23 *CR#1
24 VDDCORE_3.3
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
IN 1 = All outputs are tri-stated for test
0 = All outputs behave normally.
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
OUT Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN Clock request for SRC0, 0 = enable, 1 = disable
PWR Ground pin for the SRC outputs
OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
2
1451—01/20/09
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ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
Advance Information
SSOP Pin Description (continued)
PIN #
PIN NAME
25 VDDIO_1.5
26 SRCC1_LPR
27 SRCT1_LPR
28 GNDSRC
29 SRCC2_LPR
30 SRCT2_LPR
31 *CR#2
32 FSB_L
33 CPUC2_LPR
34 CPUT2_LPR
35 GNDCPU
36 VDDIO_1.5
37 VDDCORE_3.3
38 CPUC1_LPR
39 CPUT1_LPR
40 GNDCPU
41 VDDIO_1.5
42 CPUC0_LPR
43 CPUT0_LPR
44 CPU_STOP#
TYPE
DESCRIPTION
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
PWR Ground pin for the SRC outputs
OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC2, 0 = enable, 1 = disable
IN Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
IN Stops all CPU clocks, except those set to be free running clocks
45 CLKPWRGD#/PD_3.3
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
IN are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
46 X2
47 X1
48 VDDREF_3.3
OUT Crystal output, Nominally 14.318MHz
IN Crystal input, Nominally 14.318MHz.
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
3
1451—01/20/09
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ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
MLF Pin Configuration
Advance Information
CPU_STOP# 1
CLKPWRGD#/PD_3.3 2
X2 3
X1 4
VDDREF_3.3 5
REF 6
GNDREF 7
VDDCORE_3.3 8
FSC_L 9
TEST_MODE 10
TEST_SEL 11
SCLK_3.3 12
48 47 46 45 44 43 42 41 40 39 38 37
ICS9UMS9633
13 14 15 16 17 18 19 20 21 22 23 24
36 *CR#2
35 SRCT2_LPR
34 SRCC2_LPR
33 GNDSRC
32 SRCT1_LPR
31 SRCC1_LPR
30 VDDIO_1.5
29 VDDCORE_3.3
28 *CR#1
27 SRCT0_LPR
26 SRCC0_LPR
25 GNDSRC
48-pin MLF, 6x6 mm, 0.4mm pitch
* indicates inputs with internal pull up of ~10Kohm to 3.3V
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
4
1451—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/



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