HYMD132645B8-L Datasheet PDF - Hynix Semiconductor

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HYMD132645B8-L
Hynix Semiconductor

Part Number HYMD132645B8-L
Description 32M x 64 bits Unbuffered DDR SDRAM DIMM
Page 17 Pages


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DESCRIPTION
32Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD132645B(L)8-M/K/H/L
Hynix HYMD132645B(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD132645B(L)8-M/K/
H/L series consists of sixteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.
Hynix HYMD132645B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of
industry standard. It is suitable for easy interchange and addition.
Hynix HYMD132645B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD132645B(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 256MB (32M x 64) Unbuffered DDR DIMM based on
16Mx8 DDR SDRAM
• JEDEC Standard 184-pin dual in-line memory module
(DIMM)
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
• Data inputs on DQS centers when write (centered
DQ)
• Data strobes synchronized with output data for read
and input data for write
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• tRAS Lock-out function supported
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Factor
HYMD132645B(L)8-M
HYMD132645B(L)8-K
HYMD132645B(L)8-H
HYMD132645B(L)8-L
VDD=2.5V
VDDQ=2.5V
133MHz (*DDR266:2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
125MHz (*DDR200)
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/May. 02
1



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PIN DESCRIPTION
Pin
CK0,/CK0,CK1,/CK1,CK2,/CK2
CS0, CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A11
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
HYMD132645B(L)8-M/K/H/L
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E2PROM Address Inputs
E2PROM Clock
E2PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
PIN ASSIGNMENT
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
1
VREF
32
A5
62 VDDQ 93
VSS 124 VSS 154 /RAS
2
DQ0
33 DQ24 63
/WE
94
DQ4
125
A6
155 DQ45
3
VSS
34
VSS
64 DQ41 95
DQ5
126 DQ28 156 VDDQ
4
DQ1
35 DQ25 65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5 DQS0 36 DQS3 66
VSS
97
DM0
128 VDDQ 158
/CS1
6
DQ2
37
A4
67 DQS5 98
DQ6 129 DM3 159 DM5
7
VDD 38 VDD 68 DQ42 99
DQ7
130
A3
160 VSS
8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46
9
NC
40 DQ27 70
VDD
101
NC
132 VSS 162 DQ47
10 NC 41 A2 71 NC 102 NC 133 DQ31 163 NC
11 VSS 42 Vss 72 DQ48 103 A13* 134 CB4* 164 VDDQ
12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5* 165 DQ52
13 DQ9 44 CB0* 74 VSS 105 DQ12 136 VDDQ 166 DQ53
14 DQS1 45
CB1*
75
/CK2
106 DQ13 137
CK0
167
NC
15 VDDQ 46 VDD 76 CK2 107 DM1 138 /CK0 168 VDD
16
CK1
47 DQS8* 77 VDDQ 108
VDD
139
VSS
169 DM6
17 /CK1 48 A0 78 DQS6 109 DQ14 140 DM8* 170 DQ54
18 VSS 49 CB2* 79 DQ50 110 DQ15 141 A10 171 DQ55
19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6* 172 VDDQ
20 DQ11 51 CB3* 81
VSS 112 VDDQ 143 VDDQ 173
NC
21 CKE0 52 BA1 82 VDDID 113 BA2* 144 CB7* 174 DQ60
22 VDDQ Key 83 DQ56 114 DQ20
key 175 DQ61
23 DQ16 53 DQ32 84 DQ57 115 A12* 145 VSS 176 VSS
24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7
25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62
26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180 VDDQ
28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0
29 A7 59 BA0 90 WP 121 DQ22 151 DQ39 182 SA1
30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2
31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.3/May. 02
2



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FUNCTIONAL BLOCK DIAGRAM
HYMD132645B(L)8-M/K/H/L
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
. ./CS0
/CS1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D0
DM /CS DQS
I/O 0
I/O 1
I/O 6
D8
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D1
DM /CS DQS
I/O 0
I/O 1
I/O 6
D9
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D10
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D11
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
.
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D12
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
/CS DQS
D15
Serial PD
SCL
WP
A0 A1 A2
SA0 SA1 SA2
SDA
*Clock Wiring
Clock Input
SDRAMs
*CK0,/CK0
*CK1,/CK1
*CK2,/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per clock loading table/wiring diagrams
VDDSPD
VREF
VSS
VDDID
...... . ..= =
SPD
D0 - D15
D0 - D15
=
D0 - D15
Strap:see Note 4
BA0-BA1
A0 - A11
CKE1
/RAS
/CAS
CKE0
/WE
BA0-BA1 : SDRAMs D0 - D15
A0 - A11 : SDRAMs D0 - D15
CKE1 : SDRAMs D8 - D15
/RAS : SDRAMs D0 - D15
/CAS : SDRAMs D0 - D15
CKE : SDRAMs D0 - D7
/WE : SDRAMs D0 - D15
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown
3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5%
4. VDDID strap connections
(for memory device VDD, VDDQ) :
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ
Rev. 0.3/May. 02
3



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ABSOLUTE MAXIMUM RATINGS
HYMD132645B(L)8-M/K/H/L
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature / Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
16
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS=0V)
Unit
oC
oC
V
V
V
mA
W
oC / Sec
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
Symbol
VDD
VDDQ
VIH
VIL
VTT
VREF
Min
2.3
2.3
VREF + 0.15
-0.3
VREF - 0.04
0.49*VDDQ
Typ.
2.5
2.5
-
-
VREF
0.5*VDDQ
Max
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
Unit
V
V
V
V
V
V
Note
1
2
3
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS=0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.3/May. 02
4



HYMD132645B8-L datasheet pdf
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