HY5DV281622DTP Datasheet PDF - Hynix Semiconductor


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HY5DV281622DTP
Hynix Semiconductor

Part Number HY5DV281622DTP
Description 128M(8M x 16) GDDR SDRAM
Page 28 Pages

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HY5DV281622DTP
128M(8Mx16) GDDR SDRAM
HY5DV281622DTP
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Sep. 2003



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Revision History
Revision
No.
History
0.1 Defined target spec.
0.2 Supports Pb free parts for each speed grade
HY5DV281622DTP
Draft Date Remark
Aug. 2003
Sep. 2003
Rev. 0.2 / Sep. 2003
2



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HY5DV281622DTP
DESCRIPTION
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• 3.3V for VDD and 2.5V for VDDQ power supply
• All inputs and outputs are compatible with SSTL_2
interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Write mask byte controls by LDM and UDM
• Programmable /CAS latency 3 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 32ms
• Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS
ORDERING INFORMATION
Part No.
Power Supply
HY5DV281622DTP-33
HY5DV281622DTP-36
HY5DV281622DTP-4
HY5DV281622DTP-5
HY5DV281622DTP-6
VDD=3.3V
VDDQ=2.5V
Clock
Frequency
300MHz
275MHz
250MHz
200MHz
166MHz
Max Data Rate
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
333Mbps/pin
interface
SSTL-2
Package
400mil 66pin
TSOP-II
Note) Hynix supports Pb free parts for each speed grade with same specification, except Pb free material
We'll add "P" character after "T" for Pb free product. For example, the part number of 300MHz Pb free product is
HY5DV281622DTP-33.
Rev. 0.2 / Sep. 2003
3



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PIN CONFIGURATION
HY5DV281622DTP
VDD
1
DQ0 2
TOP VIEW
VDDQ 3
DQ1 4
DQ2 5
VSSQ
6
DQ3 7
DQ4 8
VDDQ
9
DQ5 10
DQ6 11
VSSQ
12
DQ7 13
NC 14
VDDQ
15
400mil X 875mil
LDQS
NC
16
17
66 Pin TSOP-II
0.65mm Pin Pitch
VDD
18
NC 19
LDM 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10/AP 28
A0 29
A1 30
A2 31
A3 32
VDD
33
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CLK
45 CLK
44 CKE
43 NC
42 NC
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
ROW and COLUMN ADDRESS TABLE
Items
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
8Mx16
2M x 16 x 4banks
A0 ~ A11
A0 ~ A8
BA0, BA1
A10
4K
Rev. 0.2 / Sep. 2003
4




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