HT2201 Datasheet PDF - Holtek Semiconductor


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HT2201
Holtek Semiconductor

Part Number HT2201
Description CMOS 1K 2-Wire Serial EEPROM
Page 11 Pages

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CMOS 1K 2-Wire Serial EEPROM
Features
· Operating voltage: 2.2V~5.5V
· Low power consumption
- Operation: 5mA max.
- Standby: 4mA max.
· Internal organization: 128´8
· 2-wire serial interface
· Write cycle time: 5ms max.
· Automatic erase-before-write operation
· Write operation with built-in timer
· 40-year data retention
· 106 erase/write cycles per word
· Industrial temperature range (-40°C to +85°C)
· 4-pin SIP, SOT-25 package
General Description
The HT2201 is a 1K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 1024 bits of memory are organized into 128 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
low power and low voltage operation are essential. The
HT2201 is guaranteed for 1 million erase/write cycles
and 40-year data retention.
Block Diagram
Pin Assignment
S C L I/O
C o n tro l
S D A L o g ic
M e m o ry
C o n tro l
L o g ic
A d d re s s
C o u n te r
VCC
VSS
H V P um p
X
D EEPRO M
E A rra y
C
P age B uf
YDEC
S ense A M P
R /W C o n tro l
1234
H T2201
4 S IP -A
54
12 3
H T2201
S O T -2 5 -A
Pin Description
Pin Name
I/O
SDA
I/O
SCL
I
VSS
¾
VCC
¾
Serial data inputs/output
Serial clock data input
Negative power supply, ground
Positive power supply
Description
Rev. 1.20
1 January 6, 2006



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Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Input Voltage .............................VSS-0.3V to VCC+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
Parameter
Test Conditions
VCC Conditions
VCC Operating Voltage
¾¾
ICC1 Operating Current
5V Read at 100kHz
ICC2 Operating Current
5V Write at 100kHz
VIL Input Low Voltage
¾¾
VIH Input High Voltage
¾¾
VOL Output Low Voltage
2.4V IOL=2.1mA
ILI Input Leakage Current
5V VIN=0 or VCC
ILO Output Leakage Current
5V VOUT=0 or VCC
ISTB1
Standby Current
5V VIN=0 or VCC
ISTB2
Standby Current
2.4V VIN=0 or VCC
CIN
Input Capacitance (See Note)
¾ f=1MHz 25°C
COUT
Output Capacitance (See Note) ¾ f=1MHz 25°C
Note: These parameters are periodically sampled but not 100% tested
Ta=-40°C~85°C
Min. Typ. Max. Unit
2.2
¾
¾
-1
0.7VCC
¾
¾
¾
¾
¾
¾
¾
¾ 5.5
V
¾ 2 mA
¾ 5 mA
¾ 0.3VCC
V
¾ VCC+0.5 V
¾ 0.4
V
¾ 1 mA
¾ 1 mA
¾ 4 mA
¾ 3 mA
¾ 6 pF
¾ 8 pF
Rev. 1.20
2 January 6, 2006



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A.C. Characteristics
Ta=-40°C~85°C
Symbol
Parameter
Remark
Standard Mode* VCC=5V±10%
Min. Max. Min. Max.
fSK Clock Frequency
¾ ¾ 100 ¾ 400
tHIGH
Clock High Time
¾
4000
¾
600
¾
tLOW
Clock Low Time
¾ 4700 ¾ 1200 ¾
tr
SDA and SCL Rise Time
Note
¾ 1000 ¾
300
tf SDA and SCL Fall Time Note
¾ 300 ¾ 300
After this period the
tHD:STA START Condition Hold Time
first clock pulse is
4000
¾
600
¾
generated
tSU:STA
START Condition Setup Time
Only relevant for
repeated START
condition
4000
¾
600
¾
tHD:DAT Data Input Hold Time
¾ 0¾0¾
tSU:DAT Data Input Setup Time
¾ 200 ¾ 100 ¾
tSU:STO STOP Condition Setup Time
¾
4000
¾
600
¾
tAA Output Valid from Clock
¾
¾ 3500 ¾
900
tBUF Bus Free Time
Time in which the bus
must be free before a
new transmission can
4700
¾
1200
¾
start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression
time
¾
100
¾
50
tWR Write Cycle Time
¾ ¾5¾5
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Rev. 1.20
3 January 6, 2006



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Functional Description
· Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
Memory Organization
· HT2201, 1K-bit serial EEPROM
Internally organized with 128´8-bit words, the
HT2201 requires an 8-bit data word address for ran-
dom word addressing.
Device Operations
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
D a ta a llo w e d
to c h a n g e
SDA
SCL
S ta rt A d d re s s o r
c o n d itio n a c k n o w le d g e
v a lid
N o A C K S to p
s ta te c o n d itio n
Device Addressing
The HT2201 requires an 8-bit device address word fol-
lowing a start condition to enable the chip for a read or
write operation. The device address word consist of a
mandatory one, zero sequence for the first four most
significant bits (refer to the diagram showing the Device
Address). This is common to all the EEPROM device.
The next three bits are fixed to zeros.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
1 0 1 0 0 0 0 R /W
D e v ic e A d d r e s s
Write Operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
· Read operations
The HT2201 supports three read operations, namely,
current address read, random address read and se-
quential read. During read operation execution, the
read/write select bit should be set to ²1².
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
No
Y es
N e x t O p e r a tio n
Acknowledge Polling Flow
Rev. 1.20
4 January 6, 2006




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