· Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
· HT2201, 1K-bit serial EEPROM
Internally organized with 128´8-bit words, the
HT2201 requires an 8-bit data word address for ran-
dom word addressing.
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
D a ta a llo w e d
to c h a n g e
S ta rt A d d re s s o r
c o n d itio n a c k n o w le d g e
v a lid
N o A C K S to p
s ta te c o n d itio n
The HT2201 requires an 8-bit device address word fol-
lowing a start condition to enable the chip for a read or
write operation. The device address word consist of a
mandatory one, zero sequence for the first four most
significant bits (refer to the diagram showing the Device
Address). This is common to all the EEPROM device.
The next three bits are fixed to zeros.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
1 0 1 0 0 0 0 R /W
D e v ic e A d d r e s s
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
· Read operations
The HT2201 supports three read operations, namely,
current address read, random address read and se-
quential read. During read operation execution, the
read/write select bit should be set to ²1².
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
N e x t O p e r a tio n
Acknowledge Polling Flow
4 January 6, 2006