HR2000 Datasheet PDF - Honeywell


Part Number HR2000
Description Ricmos Gate Arrays
Page 2 Pages

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• Fabricated on Honeywell’s Radiation Hardened
0.65 µmLeff RICMOS™ IV Bulk Process
• Array Sizes from 10K to 336K Available Gates (Raw)
• TTL or CMOS Compatible I/O
• Full Complement of Screening Flows
www.DataSheet4UC.oconmfigurable Multi-Port Gate Array SRAM
• Modular Custom Drop-In SRAM Capability
• Supports System Speeds Beyond 75 MHz
• Total Dose Hardness 1x106 rad(SiO2)
• Dose Rate Upset Hardness 1x109 rad(Si)/sec
• Dose Rate Survivability 1x1012 rad (Si)/sec
• Soft Error Rate 1x10-10 Errors/Bit/Day
• Neutron Fluence Hardness to 1x1014/cm2
• No Latchup
• Supports 5V Operation
The HR2000 gate arrays are performance oriented sea-
of-transistor arrays, fabricated on Honeywell’s 0.65 µm
RICMOS™ IV bulk CMOS process. The high density and
performance characteristics of the RICMOS (Radiation
Insensitive CMOS) process make possible device opera-
tion beyond 75 MHz over the full military temperature
range, even after exposure to ionizing radiation exceed-
ing 1x106 rad(SiO2). Flip-Flops have been designed for a
Soft Error Rate (SER) of less than 1x10-10 errors/bit/day in
the Adams 90% worst case environment.
Each HR2000 design is founded on our proven RICMOS
ASIC library of SSI and MSI logic elements, configurable
RAM cells and selectable I/O pads. The gate arrays
feature a global clock network capable of handling mul-
tiple clock signals with low clock skew between registers.
This family is fully compatible with Honeywell’s high
reliability screening procedures and consistent with QML
Class Q and V requirements.
Designers can choose from a wide variety of I/O types.
Output buffer options include 5 drive strengths, CMOS/
TTL levels, IEEE 1149.1 boundary scan, pull-up/pull-
down resistors, and three-state capability. Input buffers
can be selected with CMOS/TTL/Schmitt trigger levels,
IEEE 1149.1 boundary scan and pull-up/pull-down resis-
tors. Bi-directional buffers are also available.
The HR2000 family provides options for configurable
multi-port SRAMs. Word widths can be selected in single
bit increments. A variety of SRAM read and write port
options are available to serve most applications. Custom
drop-in macrocells can also be implemented to further
increase chip density.
Logic designers need not have prior experience in radia-
tion hardening. Honeywell’s VDS™ Toolkit and RICMOS
IV libraries provide the necessary guidance to achieve
first pass design success. The VDS Toolkit supports
industry standard platforms including those offered by
Mentor Graphics and Synopsys.
Honeywell can perform design translations to the HR2000
arrays from other CAD platforms. Our synthesis capabili-
ties allow customers to use familiar CAD tools and librar-
ies to map the design to Honeywell library components.
The HR2000 family of gate arrays is the right choice for your
high reliability applications demanding high density and
radiation performance. To learn more about Honeywell’s
variety of space components, call us at 612-954-2888.

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HR2000 Characteristics
Total Core Gate Count
Usable Gate Count
Maximum Die I/O
Maximum Package I/O (1)
Typical Delay—2 Input NAND
Selectable I/O
I/O Interface Levels
Typical Power Dissipation
Operating Voltage
Operating Temperature
Process Technology
Minimum Geometry
(1) Design and package dependent
HR2010 HR2065 HR2090 HR2125 HR2210 HR2340
72 176 220 252 314 372
60 172 220 216 256 320
350 ps at 5.0V
Driver, Receiver, Bi-Directional, Three-State
CMOS, TTL, Schmitt Trigger
0.65 µW/Gate/MHz, @ 5.0V
5V ± 10%
-55° C to 125° C
0.65 µm Leff / 0.8 µm Drawn
To learn more about Honeywell Solid State Electronics Center, visit our web site at
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
900171 Rev. A
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