GS8170DW36C-333 Datasheet PDF - GSI Technology


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GS8170DW36C-333
GSI Technology

Part Number GS8170DW36C-333
Description (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
Page 30 Pages

GS8170DW36C-333 datasheet pdf
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Preliminary
GS8170DW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Σ18Mb
1x1Dp CMOS I/O
200 MHz–333 MHz
1.8 V VDD
Double Late Write SigmaRAM™
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
Bottom View
Key Fast Bin Specs
Cycle Time
Symbol
tKHKH
- 333
3.0 ns
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Access Time
tKHQV
1.6 ns
Functional Description
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SigmaRAM Family Overview
GS8170DW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Rev: 2.01 5/2003
1/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



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SigmaRAM Pinouts
Preliminary
GS8170DW36/72C-333/300/250/200
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
256k x 72 Common I/O—Top View
1 2 3 4 5 6 7 8 9 10 11
DQg DQg
A
E2
A ADV A
E3
A DQb DQb
DQg DQg
Bc
Bg NC
W
A
Bb Bf DQb DQb
DQg DQg
Bh
Bd
NC
E1
NC
Be
Ba DQb DQb
(144M)
DQg DQg VSS NC NC MCL NC NC VSS DQb DQb
DQg
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQf
DQb
DQc DQc VSS VSS VSS ZQ VSS VSS VSS DQf DQf
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
DQf
DQf
DQc DQc VSS VSS VSS EP3 VSS VSS VSS DQf DQf
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQf
DQf
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
DQh DQh VSS
VSS
VSS
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MCL
VSS
VSS
VSS DQa DQa
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
DQh DQh VSS VSS VSS MCL VSS VSS VSS DQa DQa
DQd
DQh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
DQe
DQd DQd VSS NC NC MCL NC NC VSS DQe DQe
DQd DQd
NC
A NC A NC A
(72M)
(36M)
NC DQe DQe
DQd DQd
A
A
A A1 A
A
A DQe DQe
DQd DQd TMS
TDI
A
A0
A TDO TCK DQe DQe
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 2.01 5/2003
2/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



No Preview Available !

Preliminary
GS8170DW36/72C-333/300/250/200
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
512k x 36 Common I/O—Top View
1 2 3 4 5 6 7 8 9 10 11
NC NC A E2 A ADV A E3 A DQb DQb
NC NC Bc NC
A
W
A
Bb NC DQb DQb
NC NC NC Bd NC E1 NC NC Ba DQb DQb
(144M)
NC NC VSS NC NC MCL NC NC VSS DQb DQb
NC
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
DQb
DQc DQc VSS VSS VSS ZQ VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
DQc DQc VSS VSS VSS EP3 VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
NC NC V V V MCH V V V DQa DQaDDQ DDQ
DD
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DD DDQ DDQ
NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
DQd
NC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
NC
DQd DQd VSS NC NC MCL NC NC VSS NC NC
DQd DQd
NC
A NC A NC A
(72M)
(36M)
NC NC NC
DQd DQd
A
A
A A1 A
A
A NC NC
DQd DQd TMS
TDI
A
A0
A TDO TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
NC
NC
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 2.01 5/2003
3/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



No Preview Available !

Preliminary
GS8170DW36/72C-333/300/250/200
Pin Description Table
Symbol
A
ADV
Bx
W
E1
E2 & E3
EP2 & EP3
CK
CQ, CQ
DQ
Description
Address
Advance
Byte Write Enable
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Echo Clock
Data I/O
MCH Must Connect High
MCL Must Connect Low
ZQ
TCK
TDI
TDO
TMS
NC
VDD
VDDQ
VSS
Output Impedance Control
Test Clock
Test Data In
Test Data Out
Test Mode Select
No Connect
Core Power Supply
Output Driver Power Supply
Ground
Type
Input
Input
Input
Input
Input
Input
Mode Input
Input
Output
Input/Output
Input
Input
Mode Input
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Input
Input
Output
Input
Input
Input
Input
Comments
Active High
Active Low
Active Low
Active Low
Programmable Active High or Low
To be tied directly to VDD, VDDQ or VSS
Active High
Three State - Deselect via E2 or E3 False
Three State
Active High
To be tied directly to VDD or VDDQ
Active Low
To be tied directly to VSS
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
To be tied directly to VDDQ or VSS
Active High
Not connected to die or any other pin
1.8 V Nominal
1.8 V Nominal
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the
Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 2.01 5/2003
4/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/




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