GS8170DD36C-200 Datasheet PDF - GSI Technology


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GS8170DD36C-200
GSI Technology

Part Number GS8170DD36C-200
Description Double Data Rate SigmaRAM
Page 29 Pages

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GS8170DD36C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x2Lp CMOS I/O
Double Data Rate SigmaRAM™
200 MHz–333 MHz
1.8 V VDD
1.8 V I/O
Features
• Double Data Rate Read and Write mode
• Late Write; Pipelined read operation
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
SigmaRAM Family Overview
GS8170DD36 SigmaRAMs are built in compliance with the
SigmaRAM pinout standard for synchronous SRAMs. They
are 18,874,368-bit (18Mb) SRAMs. This family of wide, very
low voltage CMOS I/O SRAMs is designed to operate at the
speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Because the DDR ΣRAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR ΣRAM is always
one address pin less than the advertised index depth (e.g., the
512k x 36 has a 512k addressable index).
www.DataSheet.co.kr
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. DDR ΣRAMs incorporate rising-
and falling-edge-triggered output registers. They also utilize a
Dual Cycle Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.8 ns
Rev: 2.03 1/2005
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/



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GS8170DD36C-333/300/250/200
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
512K x 36 Common I/O—Top View (Package C)
1 2 3 4 5 6 7 8 9 10 11
NC NC A E2 A ADV A E3 A DQb DQb
NC NC MCL NC
A
W
A MCL NC DQb DQb
NC NC NC MCL NC E1 NC NC MCL DQb DQb
(144M)
NC NC VSS NC NC MCL NC NC VSS DQb DQb
NC
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
DQb
DQc DQc VSS VSS VSS ZQ VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
DQc DQc VSS VSS VSS EP3 VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
www.DataSheet.co.kr
NC
NC
VDDQ
VDDQ
VDD
MCL
VDD
VDDQ
VDDQ
DQa
DQa
NC NC VSS VSS VSS MCH VSS VSS VSS DQa DQa
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
DQd
NC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
NC
DQd DQd VSS NC NC MCL NC NC VSS NC NC
DQd DQd
NC
A NC A NC A
(72M)
(36M)
NC NC NC
DQd DQd
A
A
A A1 A
A
A NC NC
DQd DQd TMS
TDI
A MCL A TDO TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
NC
NC
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to allow alternate
use of future HSTL I/O SigmaRAMs.
Rev: 2.03 1/2005
2/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/



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GS8170DD36C-333/300/250/200
Pin Description Table
Symbol
A
ADV
W
E1
E2 & E3
EP2 & EP3
CK
CQ, CQ
DQ
MCH
MCL
ZQ
TCK
TDI
TDO
TMS
NC
VDD
VDDQ
VSS
Description
Address
Advance
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Echo Clock
Data I/O
Must Connect High
Must Connect Low
Output Impedance Control
Test Clock
Test Data In
Test Data Out
Test Mode Select
No Connect
Core Power Supply
Output Driver Power Supply
Ground
Type
Input
Input
Input
Input
Input
Mode Input
Input
Output
Input/Output
Input
Input
Mode Input
Inputwww.DataSheet.co.kr
Input
Output
Input
Input
Input
Input
Comments
Active High
Active Low
Active Low
Programmable Active High or Low
To be tied directly to VDD, VDDQ or VSS
Active High
Three State - Deselect via E2 or E3 False
Three State
Active High
To be tied directly to VDD or VDDQ
Active Low
To be tied directly to VSS
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
To be tied directly to VDDQ or VSS
Active High
Not connected to die or any other pin
1.8 V Nominal
1.8 V Nominal
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 2.03 1/2005
3/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/



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GS8170DD36C-333/300/250/200
Read Operations
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, the Double Data Rate protocol doubles the
data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In
Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The
output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to
the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only.
Double Data Rate Pipelined Read
Read
Deselect
Read
Read
Read
CK
Address
A
XX
C
D
E
F
ADV
/E1
/W
DQ
CQ
QA0
QA1
www.DataSheet.co.kr
QC0 QC1 QD0 QD1
Key
Hi-Z
Access
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Double Data Rate Write
A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both
rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address
and command.
Rev: 2.03 1/2005
4/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/




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