GS8170DD18C-250 Datasheet PDF - GSI Technology


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GS8170DD18C-250
GSI Technology

Part Number GS8170DD18C-250
Description SigmaRAM SRAM
Page 30 Pages

GS8170DD18C-250 datasheet pdf
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209-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
GS8170DD18/36C-333/300/250
18Mb Σ1x2Lp Double Data Rate
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Double Data Rate Read and Write mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 user-programmable chip enable inputs for easy depth
expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
Pipeline mode
tKHKH
tKHQV
- 333
3.0 ns
1.6 ns
SigmaRAM Family Overview
GS8170DD18/36 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage CMOS I/O SRAMs
designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's ΣRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAMfamily standard allows a user to implement the
interface protocol best suited to the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address and
read/write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.www.DataSheet.co.kr
Because the DDR ΣRAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR ΣRAM is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
In Pipeline mode, Single Data Rate (SDR) ΣRAMs incorporate
a rising-edge-triggered output register. In DDR mode, rising-
and falling-edge-triggered output registers are employed. For
read cycles, a DDR SRAM’s output data is staged at the input
of an edge-triggered output register during the access cycle and
then released to the output drivers at the next rising and
subsequent falling edge of clock.
GS817x18/36/72B ΣRAMs are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
Rev: 1.00e 6/2002
1/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



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Preliminary
GS8170DD18/36C-333/300/250
8170DD36 512K x 36 Pinout
512K x 36 Common I/O—Top View
1 2 3 4 5 6 7 8 9 10 11
A NC NC A E2 A ADV A E3 A DQb DQb
B NC NC MCL NC A W A MCL NC DQb DQb
C NC NC NC MCL NC E1 NC NC MCL DQb DQb
(144M)
D NC NC VSS NC NC MCL NC NC VSS DQb DQb
E NC DQc VDDQ VDDI VDD VDD VDD VDDI VDDQ NC DQb
F DQc DQc VSS VSS VSS ZQ VSS VSS VSS NC NC
G
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
H DQc DQc VSS VSS VSS EP3 VSS VSS VSS NC NC
J
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
K
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
L
NC
NC
VDDQ
VDDQ
VDD
MCL
VDD
VDDQ
VDDQ
DQa
DQa
M NC NC VSS VSS VSS MCH VSS VSS VSS DQa DQa
www.DataSheet.co.kr
N
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
R
DQd
NC
VDDQ
VDDI
VDD
VDD
VDD
VDDI VDDQ DQa
NC
T DQd DQd VSS NC NC MCL NC NC VSS NC NC
U
DQd DQd
NC
A NC (72M) A NC (36M) A
NC NC NC
V DQd DQd A A A A1 A A A NC NC
W
DQd DQd TMS
TDI
A MCL A TDO TCK
• 2001.03
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
NC
NC
Rev: 1.00e 6/2002
2/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



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8170DD18 1M x 18 Pinout
123
A NC NC A
Preliminary
GS8170DD18/36C-333/300/250
1M x 18 Common I/O—Top View
4 5 6 7 8 9 10 11
E2 A ADV A E3 A NC NC
B NC NC MCL NC A W A NC NC NC NC
C
NC NC NC NC NC E1
A
NC MCL NC
NC
(144M)
D NC NC VSS NC NC MCL NC NC VSS NC NC
E
NC DQb VDDQ VDDI VDD VDD VDD VDDI VDDQ NC
NC
F DQb DQb VSS VSS VSS ZQ VSS VSS VSS NC NC
G
DQb
DQb
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
H DQb DQb VSS VSS VSS EP3 VSS VSS VSS NC NC
J
DQb
DQb
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
K
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
L
NC
NC
VDDQ
VDDQ
VDD
MCL
VDD
VDDQ
VDDQ
DQa
DQa
M NC NC VSS VSS VSS MCH VSS VSS VSS DQa DQa
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N
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
R
NC
NC
VDDQ
VDDI
VDD
VDD
VDD
VDDI VDDQ DQa
NC
T NC NC VSS NC NC MCL NC NC VSS NC NC
U NC NC NC A NC A NC A NC NC NC
(72M)
(36M)
V NC NC A A A A1 A A A NC NC
W
• 2001.03
NC
NC TMS TDI
A
MCL
A
TDO TCK
NC
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
NC
Rev: 1.00e 6/2002
3/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/



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Pin Description Table
Pin Location
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W7
C7
B5
A6
K3
K1, K11
K2, K10
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
C6
A4, A8
G6, H6
W9
W4
W8
W3
J6, M6, N6
B3, C9, D6, K6, L6, P6,
T6, W6
B8, C4
Symbol
A
A
A
ADV
CK
CQ
CQ
DQ
DQ
E1
E2 & E3
EP2 & EP3
TCK
TDI
TDO
TMS
MCH
MCL
MCL
Preliminary
GS8170DD18/36C-333/300/250
Description
Address
Address
Address
Advance
Clock
Echo Clock
Echo Clock
Data I/O
Type
Input
Input
Input
Input
Input
Output
Output
Input/Output
Comments
x18 version only
x18 and x36 versions
Active High
Active High
Active High
Active Low
x18 and x36 versions
Data I/O
Chip Enable
Chip Enable
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Chip Enable Program Pin
Test Clock
Test Data In
Test Data Out
Test Mode Select
Must Connect High
Must Connect Low
Must Connect Low
Input/Output
x36 version
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Active Low
Programmable Active High or Low
Active High
Active High (all versions)
Active Low (all versions)
Active Low (x36 version)
Rev: 1.00e 6/2002
4/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/




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