GD25Q20 Datasheet PDF - GigaDevice

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GD25Q20
GigaDevice

Part Number GD25Q20
Description Dual and Quad SPI Flash
Page 30 Pages


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Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
FEATURES
4M/2M/1M/512K-bit Serial Flash
-512/256/128/64K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI:SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI:SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
Program/Erase Speed
-Page Program time:0.7ms typical
-Sector Erase time:150ms typical
-Block Erase time:0.3\0.5s typical
-Chip Erase time:3\2\1\0.5s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
Advanced security Features(1)
-Write protect all/portion of memory via software
-16-Bit Customer ID
-Enable/Disable protection with WP# Pin
-Security Architecture
-Top or Bottom, Sector or Block selection
Single Power Supply Voltage
Minimum 100,000 Program/Erase Cycles
-Full voltage range:2.7~3.6V
Note: 1.Please contact Gigadevice for details.
GENERAL DESCRIPTION
The GD25Q40/20/10/512 (4M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO),
I/O2 (WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 120MHz are supported allowing equivalent clock rates of
240MHz for Dual Output & Dual I/O read command, and 480MHz for Quad output & Quad I/O read command.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1



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Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
PIN DESCRIPTION
Pin Name
I/O
CS# I
SO (IO1)
I/O
WP# (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
I
HOLD# (IO3)
I/O
VCC
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
DI(IO0)
DO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
2



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Uniform Sector
Dual and Quad SPI Flash
MEMORY ORGANIZATION
GD25Q40
Each device has
Each block has
512K
64/32K
2K 256/128
128 16/8
8/16 -
Each sector has
4K
16
-
-
GD25Q20
Each device has
256K
1K
64
4/8
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
GD25Q10
Each device has
128K
512
32
2/4
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
GD25Q512
Each device has
64K
256
16
2
Each block has
32K
128
8
-
Each sector has
4K
16
-
-
GD25Q40/20/10/512
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Each page has
256
-
-
-
bytes
pages
sectors
blocks
3



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Uniform Sector
Dual and Quad SPI Flash
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q40 64K Bytes Block Sector Architecture
Block
Sector
7
6
……
……
2
1
0
127
……
112
111
……
96
……
……
……
……
……
……
47
……
32
31
……
16
15
……
0
GD25Q20 64K Bytes Block Sector Architecture
Block
Sector
64
3 ……
……
47
2 ……
32
31
1 ……
16
15
0 ……
0
GD25Q40/20/10/512
Address range
07F000H
……
070000H
06F000H
……
060000H
……
……
……
……
……
……
02F000H
……
020000H
01F000H
……
010000H
00F000H
……
000000H
07FFFFH
……
070FFFH
06FFFFH
……
060FFFH
……
……
……
……
……
……
02FFFFH
……
020FFFH
01FFFFH
……
010FFFH
00FFFFH
……
000FFFH
Address range
03F000H
……
……
02F000H
……
020000H
01F000H
……
010000H
00F000H
……
000000H
03FFFFH
……
……
02FFFFH
……
020FFFH
01FFFFH
……
010FFFH
00FFFFH
……
000FFFH
4



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