GAL16V8ZD Datasheet PDF - Lattice Semiconductor


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GAL16V8ZD
Lattice Semiconductor

Part Number GAL16V8ZD
Description Zero Power E2CMOS PLD
Page 19 Pages

GAL16V8ZD datasheet pdf
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GAL16V8Z
GAL16V8ZD
Zero Power E2CMOS PLD
Features
• ZERO POWER E2CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL16V8Z
— Dedicated Power-down Pin on GAL16V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS® Advanced CMOS Technology
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL16V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
CLK
I
I
I/DPP
I
I
I
I
I
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Description
The GAL16V8Z and GAL16V8ZD, at 100 µA standby current and
1D2EnSs CpRroIpPaTgIOatNion delay provides the highest speed and lowest
power combination PLD available in the market. The GAL16V8Z/
ZD is manufactured using Lattice Semiconductor's advanced zero
power E2CMOS process, which combines CMOS with Electrically
Erasable (E2) floating gate technology.
The GAL16V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL16V8. The GAL16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 15 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
DIP/SOIC
PLCC
3 1 19
I/DPP 4
1 8 I/O/Q
GAL16V8Z
I
I/O/Q
GAL16V8ZD
I6
1 6 I/O/Q
Top View
I I/O/Q
I 89
1 1 1 31 4 I/O/Q
I/CLK
I
I
I/DPP
I
I
I
I
I
GND
1 20
2 19
3 GAL 18
4 16V8Z 17
5 16V8ZD 16
6 15
7 14
8 13
9 12
10 11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
16v8zzd_03
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Specifications GAL16V8Z
GAL16V8ZD
GAL16V8Z/ZD Ordering Information
GAL16V8Z: Commercial Grade Specifications
Tpd (ns)
12
15
Tsu (ns)
10
15
Tco (ns)
8
10
Icc (mA)
55
55
55
55
55
55
Isb (µA)
100
100
100
100
100
100
Ordering #
GAL16V8Z-12QP
GAL16V8Z-12QJ
GAL16V8Z-12QS
GAL16V8Z-15QP
GAL16V8Z-15QJ
GAL16V8Z-15QS
GAL16V8ZD: Commercial Grade Specifications
Tpd (ns)
12
15
Tsu (ns)
10
15
Tco (ns)
8
10
Icc (mA)
55
55
55
55
Isb (µA)
100
100
100
100
Ordering #
GAL16V8ZD-12QP
GAL16V8ZD-12QJ
GAL16V8ZD-15QP
GAL16V8ZD-15QJ
Package
20-Pin Plastic DIP
20-Lead PLCC
20-Lead SOIC
20-Pin Plastic DIP
20-Lead PLCC
20-Lead SOIC
Package
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
Part Number Description
XXXXXXXX _ XX X X X
Device Name
GAL16V8Z (Zero Power ITD)
GAL16V8ZD (Zero Power DPP)
Speed (ns)
Active Power
Q = Quarter Power
Grade
Blank = Commercial
Package
P = Plastic DIP
J = PLCC
S = SOIC
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Specifications GAL16V8Z
GAL16V8ZD
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL16V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using the standard GAL16V8 JEDEC fuse pattern generated
by the logic compilers for the GAL16V8ZD, special attention must
be given to pin 4 (DPP) to make sure that it is not used as one of
the functional inputs.
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Registered Mode
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/Os are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
Specifications GAL16V8Z
GAL16V8ZD
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
CLK
DQ
XOR Q
OE
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
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