FEDL9058E Datasheet PDF - LAPIS

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FEDL9058E
LAPIS

Part Number FEDL9058E
Description 132-Channel LCD Driver
Page 30 Pages


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LAPIS Semiconductor
FEDL9058E-01
Issue Date: April. 13, 2007
ML9058E
132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
GENERAL DESCRIPTION
The ML9058E is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot
matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).
Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the
ML9058E makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips.
Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is
possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip,
it is possible to construct a graphic display system with a maximum of 65 132 dots. The display can be expanded
further using two chips. However, the ML9058E is not used in a multiple chip configuration when a line reversal
drive is set.
The ML9058E is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of
its features, and is therefore suitable for displays in battery-operated portable equipment.
The ML9058E has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of
up to 65 132 dots.
FEATURES
Direct display of the RAM data using the bit map method
Display RAM data “1” ... Dot is displayed
Display RAM data “0” ... Dot is not displayed (during forward display)
Display RAM capacity
65 132 = 8580 bits
LCD Drive circuits
65 common outputs, 132 segment outputs
MPU interface: Can select an 8-bit parallel or serial interface
Built-in voltage multiplier circuit for the LCD drive power supply
Built-in LCD drive voltage adjustment circuit
Built-in LCD drive bias generator circuit
Can select frame reversal drive or line reversal drive by command
Built-in oscillator circuit (Internal RC oscillator/external clock input)
A variety of commands
Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page
address, set display start address, etc.
Power supply voltage
Logic power supply: VDD-VSS = 3.7 V to 5.5 V
Voltage multiplier reference voltage: VIN-VSS = 3.7 V to 5.5 V
(2- to 4-time multiplier available)
LCD Drive voltage: VBI-VSS = 6.0 to 18 V
Package: Gold bump chip (Bump hardness: Low, DV)
: Gold bump chip (Bump hardness: High, CV)
This device is not resistant to radiation and light.
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LAPIS Semiconductor
BLOCK DIAGRAM
VDD
V1
V2
V3
V4
V5
VSS
VS1–
VS2–
VC3+
VC4+
VC5+
VC6+
VOUT
VIN
VR
VRS
IRS
SEGMENT
Drivers
COMMON
Drivers
Common Output state
selection circuit
Display data latch circuit
Display data RAM
65 132
Column address circuit
Bus holder
Command decoder
MPU lnterface
Status
FEDL9058E-01
ML9058E
FRS
FR
CL
DOF
M/S
CLS
TEST1
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LAPIS Semiconductor
FEDL9058E-01
ML9058E
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Bias voltage
Voltage multiplier output
voltage
Symbol
VDD
VBI
VOUT
Voltage multiplier reference
voltage
VIN
Input voltage
Storage temperature range
VI
TSTG
Condition
Tj = 25°C
Tj = 25°C
Tj = 25°C
2-time multiplication
3-time multiplication
4-time multiplication
Tj = 25°C
Chip
Tj:Chip surface temperature
Rated value
–0.3 to +6.5
–0.3 to +20
–0.3 to +20
–0.3 to +5.5
–0.3 to +5.5
–0.3 to +5.0
–0.3 to VDD+0.3
–55 to +125
VSS = 0 V
Unit Applicable pins
V VDD
V V1 to V5
V VOUT
V VIN
V All inputs
°C —
RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Bias voltage
Symbol
VDD
VBI
Voltage multiplier reference
voltage
VIN
Voltage multiplier output
voltage
Operating temperature range
VOUT
TJOP
Condition
2-time multiplication
3-time multiplication
4-time multiplication
External input
Rated value
3.7 to 5.5
6 to 18
3.7 to 5.5
3.7 to 5.5
3.7 to 4.5
6.0 to 18
–40 to +85
VSS = 0 V
Unit Applicable pins
V VDD
V V1 to V5
V VIN
V VOUT
°C —
Note 1: The electrical characteristics are influenced by COG trace resistance. This LSI always has to
be evaluated before using.
VOUT
VCC
GND
System (MPU)
VIN
VDD
VSS
ML9058E
V1 to V5
Note 2: The voltages VDD, V1 to V5, and VOUT are values taking VSS = 0 V as the reference.
Note 3: The highest bias potential is V1 and the lowest is VSS.
Note 4: Always maintain the relationship V1 V2 V3 V4 V5 VSS among these voltages.
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LAPIS Semiconductor
FEDL9058E-01
ML9058E
Note 5:
Note 6:
When using an external power supply, follow the procedure for power application.
When applying external power to the VOUT pin only, apply VOUT after VDD.
When applying external power to the V1 pin only, apply V1 after VDD.
When applying external power to the V1 pin to V5 pin, apply V1 to V5 after VDD.
Note that the above (Note 4) must be satisfied including transient state at power application.
When using an external power supply, follow the procedure for power removal described
below.
When external power is in use for the VOUT pin only, remove VOUT after VDD.
When external power is in use for the V1 pin only, remove V1 after VDD.
When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after VDD.
Note that the above (Note 4) must be satisfied including transient state at power removal.
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