FAN6751 Datasheet PDF - Fairchild Semiconductor

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FAN6751
Fairchild Semiconductor

Part Number FAN6751
Description Highly Integrated Green-Mode PWM Controller
Page 13 Pages


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AN-6073
FAN6751 — Highly Integrated Green-Mode PWM Controller
Introduction
This application note describes a detailed design strategy for
a high-efficiency, compact flyback converter. Design
considerations and mathematical equations are presented as
well as guidelines for a printed circuit board layout. The
highly integrated FAN6751 series of PWM controllers
provides several features to enhance the performance for
LCDM/TV, NB, and adapters.
The green-mode function includes off-time modulation and
burst mode to reduce the PWM frequency at light-load and
in no-load conditions. To avoid acoustic noise problems, the
minimum PWM frequency is set above 18KHz. This green-
mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss due to
bleeding resistors is also eliminated. Built-in synchronized
slope compensation achieves stable peak-current-mode
control. The proprietary external line compensation ensures
constant output power limit over a wide AC input voltage
range, from 90VAC to 264VAC.
FAN6751 provides many protection functions, as shown in
Table 1. In addition to cycle-by-cycle current limiting, the
internal open-loop protection circuit ensures safety should
an open-loop or output short-circuit failure occur.
Features
ƒ High-Voltage Startup
ƒ Low Operating Current: 4mA
ƒ Linearly Decreasing PWM Frequency to 18KHz
ƒ Fixed PWM Frequency: 65KHz
ƒ Peak-Current-Mode Control
ƒ Cycle-by-Cycle Current Limiting
ƒ Leading-Edge Blanking (LEB)
ƒ Synchronized Slope Compensation
ƒ Internal Open-loop Protection
ƒ GATE Output Maximum Voltage Clamp: 18V
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ VDD Over-Voltage Protection (OVP)
ƒ Internal Recovery Circuit (OVP, OLP)
ƒ Internal Sense Short-Circuit Protection
ƒ External Constant Power Limit (Full AC Input Range)
ƒ Internal OTP Sensor with Hysteresis
ƒ Built-in 5ms Soft-Start Function
ƒ Built-in VIN Pin Pull HIGH (> 4.7V) Recovery
Function for Second-Side Output OVP
ƒ Brownout Protection with Hysteresis
Applications
General-purpose, switch-mode power supplies and flyback
power converters, including:
ƒ Power Adapters
ƒ Open-frame SMPS
ƒ LCD Monitor/TV
SOP-8
GND
FB
NC
HV
1
2
3
4
8 GATE
7 VDD
6 SENSE
5 VIN
Figure 1. Pin Configuration (Top View)
Table 1. Protection Functions of FAN6751 Series
Part Number
FAN6751MRMY
FAN6751HLMY
OVP (VDD)
Recovery
Latch
OLP (FB)
Recovery
Latch
Pull-High
Protection (VIN)
Recovery
Latch
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
OTP
(Internal)
Recovery
Recovery
SCP
(SENSE)
Recovery
Recovery
PWM
Frequency
65KHz
100KHz
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AN-6073
APPLICATION NOTE
Typical Application
EMI
Filter
Fuse
C2
AC
INPUT
BD1
CBulk
R1 RHV
47
HV VDD
RSn1 CSn1
D1 DSn
CVDD
T1
RSn2 CSn2
Lp
D2
CO
5 VIN
R2
2
FB
RFB
CFB
NC
3
GATE 8 Rg
SENSE 6
GND
1
RLF
CLF
Q1 PC817
RS KA431
Rd
C1
Cp
R1
R3
R2
VO
Block Diagram
Figure 2. Typical Application
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
Figure 3. Functional Block Diagram
2
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AN-6073
APPLICATION NOTE
Internal Block Operation
Startup and Soft-Start Circuitry
When power is turned on, the internal high-voltage startup
current (typically 2mA) charges the hold-up capacitor C1
through startup resistor RHV. RHV can be directly connected
by VBULK to the HV pin. The built-in 5ms soft-start circuit
starts when the VDD pin reaches the start threshold voltage
VDD-ON. Soft-start helps reduce the inrush current, the startup
current spike, and output voltage overshoot during the
startup period, as shown in Figure 4. When VDD reaches
VDD-ON, the internal high-voltage startup current is switched
off and the supply current is drawn from the auxiliary
winding of the main transformer, as shown in Figure 5.
VDD
SQ
R
Soft
Driver
Soft Start
8 GATE
6 Sense
Figure 4. Soft-start Circuit
Figure 6. UVLO Specification
Under-Voltage Lockout (UVLO)
The FAN6751 has a voltage detector on the VDD pin to
ensure that the chip has enough power to drive the
MOSFET. Figure 7 shows a hysteresis of the turn-on and
turn-off threshold levels and an open-loop-release voltage.
Figure 5. Startup Circuit for Power Transfer
If a shorter startup time is required, a two-step startup
circuit, as shown Figure 6, is recommended. In this circuit, a
smaller capacitor C1 can be used to reduce startup time. The
energy supporting the FAN6751 after startup is mainly from
a larger capacitor C2. If a shorter releasing latch mode time
is required, a DHV and RHV can be directly connected by VAC
to the HV pin.
When the supply current is drawn from the transformer, it
draws a leakage current of about 1µA from HV pin. The
maximum power dissipation of the RHV is:
PRHV = IHV LC(Typ.)2 × RHV
= IμA2 ×100KΩ ≅ 0.1μW
(1)
where
IHV-LC is the supply current drawn from HV pin, and
RHV is 100K.
Figure 7. UVLO Specification
The turn-on and turn-off thresholds are internally fixed at
16.5V and 10.5V. During startup, the VDD’s capacitor must
be charged to 16.5V to enable the IC. The capacitor
continues to supply the VDD until the energy can be
delivered from the auxiliary winding of the main
transformer. The VDD must not drop below 10.5V during the
startup sequence.
To further limit the input power under a short-circuit or
open-loop condition, a special two-step UVLO mechanism
prolongs the discharge time of the VDD capacitor. Figure 8
shows the traditional UVLO method along with the special
two-step UVLO method. In the two-step UVLO mechanism,
an internal sinking current, IDD-OLP, pulls the VDD voltage
toward the VDD-OLP. This sinking current is disabled after the
VDD drops below VDD-OLP; after which, the VDD voltage is
again charged towards VDD-ON. With the addition of the two-
step UVLO mechanism, the average input power during a
short-circuit or open-loop condition is greatly reduced. As a
result, over-heating does not occur.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
3
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AN-6073
Figure 8. UVLO Effect
FB Input
The FAN6751 is designed for peak-current-mode control. A
current-to-voltage conversion is done externally with a
current-sense resistor RS. Under normal operation, the FB
level controls the peak inductor current:
VSENSE
= Ipk
× RS
=
VFB
4
0.6
(2)
where VFB is the voltage on FB pin and 4 is an internal
divider ratio.
When VFB is less than 0.6V, the FAN6751 terminates the
output pulses.
APPLICATION NOTE
down at no load. The value of the biasing resistor Rb is
determined as:
Vo VD VZ K 1.5mA
Rb
where:
(3)
VD is the drop voltage of photodiode, approximately 1.2V;
VZ is the minimum operating voltage, 2.5V of the shunt
regulator; and
K is the current transfer rate (CTR) of the opto-coupler.
For an output voltage VO=5V with CTR=100%, the
maximum value of Rb is 860.
Green Mode Operation
Green mode includes off-time modulation and burst mode to
reduce the PWM frequency at light-load and in no-load
conditions. The feedback voltage of the FB pin is taken as a
reference. When the feedback voltage is lower than VFB-N,
the PWM frequency decreases. Because most losses in a
switching-mode power supply are proportional to the PWM
frequency, the off-time modulation reduces the power
consumption of the power supply at light-load and no-load
conditions. Figure 10 is the PWM frequency is 65KHz at
nominal load and decreases to 18KHz at light load.
Frequency
Fosc:65KHz
PWM Frequency
Fosc:18KHz
VFB-ZDC
VFB-G
VFB-N
Figure 10. PWM Frequency vs. FB Voltage
Figure 9. Feedback Circuit
Figure 9 is a typical feedback circuit consisting mainly of a
shunt regulator and an opto-coupler. R1 and R2 form a
voltage divider for the output voltage regulation. R3 and C1
are adjusted for control-loop compensation. A small-value
RC filter (e.g. RFB= 100, CFB= 1nF) placed on the FB pin
to the GND can further increase the stability. The maximum
sourcing current of the FB pin is 1.5mA. The phototransistor
must be capable of sinking this current to pull FB level
The power supply enters “burst mode” in no-load
conditions. As shown in Figure 11 and Figure 12, when VFB
drops below VFB-ZDC, the PWM output is shuts off and the
output voltage drops at a rate dependent on load current.
This causes the feedback voltage to rise. Once VFB exceeds
VFB-ZDC, the internal circuit starts to provide switching pulse.
The feedback voltage then falls and the process repeats.
Burst mode operation alternately enables and disables
switching of the MOSFET, reducing the switching losses in
standby mode.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
4
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