EDI88512CA-XMXG Datasheet PDF - Microsemi

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EDI88512CA-XMXG
Microsemi

Part Number EDI88512CA-XMXG
Description 512Kx8 Plastic Monolithic SRAM CMOS
Page 9 Pages

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EDI88512CA-XMXG
WPS512K8X-XRJXG
512Kx8 Plastic Monolithic SRAM CMOS
FEATURES
 512Kx8 bit CMOS Static
 Random Access Memory
• Access Times of 17, 20, 25ns
• Data Retention Function (LPA version)
• Extended Temperature Testing
• Data Retention Functionality Testing
 36 lead JEDEC Approved Revolutionary Pinout
• Plastic SOJ (Package 319)
 Single +5V (±10%) Supply Operation
 RoHS compliant
WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to
capitalize on the cost advantage of using a plastic component while
not sacricing all of the reliability available in a full military device.
Extended temperature testing is performed with the test patterns
developed for use on WEDC’s fully compliant 512Kx8 SRAMs.
WEDC fully characterizes devices to determine the proper test
patterns for testing at temperature extremes. This is critical because
the operating characteristics of device change when it is operated
beyond the commercial guarantee a device that operates reliably
in the eld at temperature extremes. Users of WEDC’s ruggedized
plastic benet from WEDC’s extensive experience in characterizing
SRAMs for use in military systems.
WEDC ensures Low Power devices will retain data in Data
Retention mode by characterizing the devices to determine the
appropriate test conditions. This is crucial for systems operating
at -40°C or below and using dense memories such as 512Kx8s.
WEDC’s ruggedized plastic SOJ is footprint compatible with
WEDC’s full military ceramic 36 pin SOJ.
FIGURE 1 – PIN CONFIGURATION
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
CS# 6
I/O0 7
I/O1 8
VCC 9
VSS 10
I/O2 11
I/O3 12
WE# 13
A5 14
A6 15
A7 16
A8 17
A9 18
36pin
Revolutionary
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE#
30 I/O7
29 I/O6
28 VSS
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
AØ-18
WE#
CS#
OE#
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 11
1
PIN Description
I/O0-7
A0-18
WE#
CS#
OE#
VCC
VSS
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/OØ-7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

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