EDI88512CA Datasheet PDF - Microsemi

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EDI88512CA
Microsemi

Part Number EDI88512CA
Description 512Kx8 Monolithic SRAM
Page 10 Pages


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EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
 Access Times of 15, 17, 20, 25, 35, 45, 55ns
 Data Retention Function (LPA version)
 TTL Compatible Inputs and Outputs
 Fully Static, No Clocks
 Organized as 512Kx8
 Commercial, Industrial and Military Temperature Ranges
 32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
 36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
 Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. All 32 pin packages are pin for pin
upgrades for the single chip enable 128K x 8, the EDI88128CS.
Pins 1 and 30 become the higher order addresses.
The 36 pin revolutionary pinout also adheres to the JEDEC
standard for the four megabit device. The center pin power and
ground pins help to reduce noise in high performance systems.
The 36 pin pinout also allows the user an upgrade path to the
future 2Mx8.
A Low Power version with Data Retention (EDI88512LPA) is
also available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
*This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
36 PIN
TOP VIEW
A0 1
36 NC
A1 2
35 A18
A2 3
34 A17
A3 4
33 A16
A4 5
32 A15
CS# 6
31 OE#
I/O0 7
30 I/O7
I/O1 8
Vcc 9
Vss 10
36 pin
Revolutionary
29
28
27
I/O6
Vss
Vcc
I/O2 11
26 I/O5
I/O3 12
25 I/O4
WE# 13
24 A14
A5 14
23 A13
A6 15
22 A12
A7 16
21 A11
A8 17
20 A10
A9 18
19 NC
32 PIN
TOP VIEW
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 pin
Evolutionary
32 Vcc
31 A15
30 A17
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
I/O0-7
A0-18
WE#
CS#
OE#
VCC
VSS
NC
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
BLOCK DIAGRAM
Memory Array
A0-18
WE#
CS#
OE#
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



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EDI88512CA
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Voltage on any pin relative to Vss
-0.5 to 7.0
V
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
0 TA +70
-40 TA +85
-55 TA +125
-65 TA +150
1.5
°C
°C
°C
°C
W
Output Current
20 mA
Junction Temperature, TJ
175 °C
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OE# CS# WE#
XHX
HLH
L LH
XLL
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc1
Icc1
Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ Max Unit
5.0 5.5
V
00V
— VCC + 0.3 V
— +0.8 V
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Condition
Max Unit
Address Lines
CI VIN = Vcc or Vss, f = 1.0MHz 12 pF
Data Lines
CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF
These parameters are sampled, not 100% tested.
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
Symbol
ILI
ILO
ICC1
ICC2
ICC3
VOL
VOH
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C to +125°C)
Conditions
VIN = 0V to VCC
VI/O = 0V to VCC
WE#, CS# = VIL, II/O = 0mA, Min Cycle
CS# VIH, VIN VIL, VIN VIH
CS# VCC -0.2V
VIN Vcc -0.2V or VIN 0.2V
IOL = 6.0mA
IOH = -4.0mA
(17ns)
(20 -55ns)
CA
LPA
Min
-10
-10
2.4
Max Units
10 μA
10 μA
250 mA
225 mA
60 mA
25 mA
20 mA
0.4 V
—V
AC TEST CONDITIONS
Figure 1
Q
255Ω
Figure 2
Vcc
480Ω
30pF
Q
255Ω
Vcc
480Ω
5pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
VSS to 3.0V
5ns
1.5V
Figure 1
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



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EDI88512CA
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, Vss = 0V, -55°C TA +125°C)
Symbol
Parameter
JEDEC Alt.
Read Cycle Time
tAVAV
tRC
Address Access Time
Chip Enable Access Time
tAVQV
tELQV
tAA
tACS
Chip Enable to Output in Low Z (1)
tELQX
tCLZ
Chip Disable to Output in High Z (1)
tEHQZ
tCHZ
Output Hold from Address Change
tAVQX
tOH
Output Enable to Output Valid
tGLQV
tOE
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
Output Disable to Output in High Z(1) tGHQZ
1. This parameter is guaranteed by design but not tested.
tOHZ
15ns
Min Max
15
15
15
2
07
0
8
0
07
17ns
Min Max
17
17
17
3
07
0
8
0
07
20ns
Min Max
20
20
20
3
08
0
10
0
08
25ns
Min Max
25
25
25
3
0 10
0
12
0
0 10
35ns
Min Max
35
35
35
3
0 15
0
15
0
0 15
45ns
Min Max
45
45
45
3
0 20
0
25
0
0 20
55ns
Min Max
55
55
55
3
0 20
0
30
0
0 20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, -55°CTA +125°C)
Symbol
Parameter
JEDEC Alt.
Write Cycle Time
tAVAV
tWC
Chip Enable to End of Write
tELWH
tELEH
tCW
tCW
Address Setup Time
tAVWL
tAVEL
tAS
tAS
Address Valid to End of Write
tAVWH
tAVEH
tAW
tAW
Write Pulse Width
tWLWH
tWLEH
tWP
tWP
Write Recovery Time
tWHAX
tEHAX
tWR
tWR
Data Hold Time
tWHDX
tEHDX
tDH
tDH
Write to Output in High Z (1)
tWLQZ
tWHZ
Data to Write Time
tDVWH
tDVEH
tDW
tDW
Output Active from End of Write (1)
tWHQX
tWLZ
1. This parameter is guaranteed by design but not tested.
15ns
Min Max
15
13
13
0
0
13
13
13
13
0
0
0
0
08
8
8
0
17ns
Min Max
17
14
14
0
0
14
14
14
14
0
0
0
0
08
8
8
0
20ns
Min Max
20
15
15
0
0
15
15
15
15
0
0
0
0
08
10
10
0
25ns
Min Max
25
17
17
0
0
17
17
17
17
0
0
0
0
0 10
12
12
0
35ns
Min Max
35
25
25
0
0
25
25
25
25
0
0
0
0
0 25
20
20
0
45ns
Min Max
45
30
30
0
0
30
30
30
30
0
0
0
0
0 30
25
25
0
55ns
Min Max
55
50
50
0
0
50
50
45
45
0
0
0
0
0 30
40
30
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



No Preview Available !

ADDRESS
DATA I/O
EDI88512CA
FIGURE 2 – TIMING WAVEFORM – READ CYCLE
tAVAV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA 1
DATA 2
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
ADDRESS
CS#
OE#
DATA OUT
tAVAV
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tEHQZ
tGHQZ
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE – WE# CONTROLLED
ADDRESS
CS#
WE#
DATA IN
DATA OUT
tAVAV
tAVWL
tAVWH
tELWH
tWHAX
tWLWH
tWLQZ
tDVWH
tWHDX
DATA VALID
tWHQX
HIGH Z
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE – CS# CONTROLLED
ADDRESS
CS#
WE#
DATA IN
DATA OUT
tAVAV
tAVEL
tAVEH
tELEH
tWLEH
tEHAX
tDVEH
tEHDX
DATA VALID
HIGH Z
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



EDI88512CA datasheet pdf
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EDI88512CA pdf
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