EDI88512C Datasheet PDF - Microsemi

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EDI88512C
Microsemi

Part Number EDI88512C
Description 512Kx8 Monolithic SRAM
Page 8 Pages


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EDI88512C
512Kx8 Monolithic SRAM, CMOS
FEATURES
 512Kx8 bit CMOS Static
 Random Access Memory
• Access Times of 70, 85, 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
 32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic SOJ (Package 140)
 Single +5V (±10%) Supply Operation
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. Both the DIP and CSOJ packages
are pin for pin upgrades for the single chip enable 128K x 8, the
EDI88128C. Pins 1 and 30 become the higher order addresses.
A Low Power version with Data Retention (EDI88512LP) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
* This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32 PIN
TOP VIEW
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 pin
Evolutionary
32 Vcc
31 A15
30 A17
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
I/O0-7
A0-18
WE#
CS#
OE#
VCC
VSS
NC
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
A0-18
WE#
CS#
OE#
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 13
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



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EDI88512C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
Value
-0.5 to 7.0
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
Unit
V
°C
°C
°C
°C
W
mA
°C
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
OE# CS# WE#
Mode
Output
Power
X
H
X
Standby
High Z
ICC2, ICC3
H
L
H Output Deselect High Z
ICC1
L LH
Read
Data Out
ICC1
XLL
Write
Data In
ICC1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ Max Unit
5.0 5.5
V
00V
— VCC +0.5 V
— +0.8 V
CAPACITANCE
TA = +25°C
Parameter
Address Lines
Data Lines
Symbol
CI
CO
Condition
VIN = Vcc or Vss, f = 1.0MHz
VOUT = Vcc or Vss, f = 1.0MHz
These parameters are sampled, not 100% tested.
Max Unit
12 pF
14 pF
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
Symbol
ILI
ILO
ICC1
ICC2
ICC3
VOL
VOH
DC CHARACTERISTICS
VCC = 5V, -55°C *TA +125°C
Conditions
VIN = 0V to VCC
VI/O = 0V to VCC
WE#, CS# = VIL, II/O = 0mA, Min Cycle (70-100ns)
CS# VIH, VIN VIL, VIN VIH
CS# VCC -0.2V
VIN Vcc -0.2V or VIN 0.2V
IOL = 2.1mA
IOH = -1.0mA
C
LP
AC TEST CONDITIONS
Min Typ* Max Units
— — ±10 μA
— — ±10 μA
— 45 75 mA
— 3 10 mA
— — 5 mA
— — 2 mA
— — 0.4 V
2.4 — — V
Figure 1
Q
255Ω
Figure 2
Vcc
480Ω
30pF
Q
255Ω
Vcc
480Ω
5pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
VSS to 3.0V
5ns
1.5V
Figure 1
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 13
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



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EDI88512C
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – READ CYCLE
VCC = 5.0V, Vss = 0V, -55°C TA +125°C
Symbol
70ns
85ns
JEDEC
Alt.
Min
Max
Min
Max
tAVAV
tRC
70
85
tAVQV
tAA
70
85
tELQV
tACS
70
85
tELQX
tCLZ
10
10
tEHQZ
tCHZ
25
30
tAVQX
tOH
10
10
tGLQV
tOE
35
45
tGLQX
tOLZ
5
5
tGHQZ
tOHZ
0
25
0
30
100ns
Min Max
100
100
100
10
30
10
50
5
0 30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5.0V, VSS = 0V, -55°C TA +125°C
Symbol
JEDEC
Alt.
tAVAV
tWC
tELWH
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tCW
tCW
tAS
tAS
tAW
tAW
tWLWH
tWLEH
tWP
tWP
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
70ns
Min Max
70
60
60
0
0
65
65
50
50
0
0
0
0
0 25
40
30
5
85ns
Min Max
85
70
70
0
0
70
70
55
55
0
0
0
0
0 30
40
35
0
100ns
Min Max
100
80
80
0
0
80
80
60
60
0
0
0
0
0 30
40
40
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 13
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



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ADDRESS
DATA I/O
EDI88512C
FIGURE 2 – TIMING WAVEFORM – READ CYCLE
tAVAV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA 1
DATA 2
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
ADDRESS
CS#
OE#
DATA OUT
tAVAV
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tEHQZ
tGHQZ
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE – WE# CONTROLLED
ADDRESS
CS#
WE#
DATA IN
DATA OUT
tAVWL
tAVAV
tAVWH
tELWH
tWHAX
tWLWH
tWLQZ
tDVWH
tWHDX
DATA VALID
tWHQX
HIGH Z
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE – CS# CONTROLLED
ADDRESS
CS#
WE#
DATA IN
DATA OUT
tAVAV
tAVEL
tAVEH
tELEH
tWLEH
tEHAX
tDVEH
tEHDX
DATA VALID
HIGH Z
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 13
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp



EDI88512C datasheet pdf
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