EDI88128CS Datasheet PDF - White Electronic Designs

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EDI88128CS
White Electronic Designs

Part Number EDI88128CS
Description 128Kx8 Monolithic SRAM
Page 9 Pages

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White Electronic Designs
EDI88128CS
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
„ Access Times of 15*, 17, 20, 25, 35, 45, 55ns
„ CS# and OE# Functions for Bus Control
„ 2V Data Retention (EDI88128LPS)
„ TTL Compatible Inputs and Outputs
„ Fully Static, No Clocks
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
„ Single +5V (±10%) Supply OperationThe
EDI88128CS is a high speed, high performance,
128Kx8 megabit density Monolithic CMOS Static
RAM.
„ Organized as 128Kx8
„ Commercial, Industrial and Military Temperature
Ranges
„ Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 400 mil (Package 102)
• 32 pin Ceramic DIP, 600 mil (Package 9)
The device has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word. An
automatic power down feature permits the on-chip circuitry
to enter a very low standby mode and be brought back into
operation at a speed equal to the address access time.
ALow Power version with 2V Data Retention (EDI88128LPS)
is also available for battery back-up opperation. Military
product is available compliant to MIL-PRF-38535.
• 32 lead Ceramic ZIP (Package 100)
• 32 lead Ceramic SOJ (Package 140)
* 15ns access time is advanced information, contact factory for availability.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
32 LCC
32 FLATPACK
TOP VIEW
32 ZIP
TOP VIEW
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 NC
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
NC 1
A16 3
A14 5
A12 7
A7 9
A6 11
A5 13
A4 15
A3 17
A2 19
A1 21
A0 23
I/O0 25
I/O1 27
I/O2 29
VSS 31
2 VCC
4 A15
6 NC
8 WE#
10 A13
12 A8
14 A9
16 A11
18 OE#
20 A10
22 CS#
24 I/O7
26 I/O6
28 I/O5
30 I/O4
32 I/O3
A0-16
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
A0-16 Address Inputs
WE# Write Enable
CS# Chip Select
OE# Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS#
OE#
White Electronic Designs Corp. reserves the right to change products or specications without notice.
February 2000
Rev. 10
1 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com

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