EDI88128C Datasheet PDF - White Electronic Designs

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EDI88128C
White Electronic Designs

Part Number EDI88128C
Description 128Kx8 MONOLITHIC SRAM
Page 8 Pages


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White Electronic Designs
EDI88128C
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
„ Access Times of 70, 85, 100ns
„ Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
„ 2V Data Retention (LP Versions)
„ CS# and OE# Functions for Bus Control
„ TTL Compatible Inputs and Outputs
„ Fully Static, No Clocks
„ Organized as 128Kx8
„ Industrial, Military and Commercial Temperature
Ranges
„ Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
„ Single +5V (±10%) Supply Operation
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simpliy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bi-
directional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
Top View
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 NC/CS2*
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PIN DESCRIPTION
I/O0-7
Data Inputs/Outputs
A0-16
Address Inputs
WE# Write Enable
CS1#, CS2
Chip Selects
OE# Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
1 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com



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EDI88128C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
-0.5 to 7.0
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
Unit
V
°C
°C
°C
°C
W
mA
°C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
TA = +25°C
Parameter
Address Lines
Input/Output Lines
Symbol
CI
CO
Condition
VIN = VCC or VSS, f = 1.0MHz
VOUT = VCC or VSS, f = 1.0MHz
These parameters are sampled, not 100% tested.
Max Unit
12 pF
14 pF
TRUTH TABLE
OE# CS1# CS2# WE#
Mode
XHXX
Standby
XXLX
Standby
X X L X Output Deselect
H L H H Output Deselect
L LHH
Read
XLHL
Write
Output
High Z
High Z
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Icc1
Icc1
Icc1
Recommended Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ Max Unit
5.0 5.5
V
00V
— VCC +0.5 V
— +0.8 V
DC CHARACTERISTICS
VCC = 5V, -55°C TA +125°C
Parameter
Symbol Conditions
Min Typ Max Units
Input Leakage Current
ILI VIN = 0V to VCC
-5 — +5 μA
Output Leakage Current
ILO VI/O = 0V to VCC, CS1# VIH and/or CS2# VIL
-10 — +10 μA
Operating Power Supply Current
ICC1
WE#, CS1# = VIL, II/O = 0mA, Min Cycle
CS2# = VIH
(70-85ns)
(100ns)
120 mA
110 mA
Standby (TTL) Power Supply Current ICC2 CS1# VIH and/or CS2# VIL, VIN VIH or VIL
10 mA
Full Standby Power Supply Current
ICC3
CS1# VCC -0.2V and/or CS2# VCC+0.2V
VIN VCC -0.2V or VIN 0.2V
C
LP
1
5
1
mA
mA
Output Low Voltage
VOL IOL = 2.1mA
— — 0.4 V
Output High Voltage
VOH IOH = -1.0mA
2.4 — — V
NOTE: DC test conditions : VIL = 0.3V, VIH = VCC -0.3V
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
2 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com



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White Electronic Designs
EDI88128C
AC Characteristics – Read Cycle
VCC = 5V, VSS = 0V, -55°C TA +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
Symbol
JEDEC
tAVAV
tAVQV
tELQV
tSHQV
tELQX
tSHQX
tEHQZ
tSLQZ
tAVQX
tGLQV
tGLQX
tGHQZ
Alt.
tRC
tAA
tACS
tACS
tCLZ
tCLZ
tCHZ
tCHZ
tOH
tOE
tOLZ
tOHZ
70ns
Min Max
70
70
70
70
3
3
30
30
3
25
0
0 30
85ns
Min Max
85
85
85
85
3
3
30
30
3
30
0
0 30
1. This parameter is guaranteed by design but not tested.
100ns
Min Max
100
100
100
100
3
3
30
30
3
50
0
0 30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Test Conditions
Figure 1
Q
255Ω
Figure 2
Vcc
480Ω
30pF
Q
255Ω
Vcc
480Ω
5pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
3 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com



No Preview Available !

White Electronic Designs
EDI88128C
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5V, VSS = 0V, -55°C TA +125°C
Parameter
Symbol
JEDEC Alt.
70ns
Min Max
85ns
Min Max
Write Cycle Time
tAVAV
tWC
70
85
Chip Select to End of Write
tELWH
tELEH
tSHWH
tSHSL
tCW
tCW
tCW
tCW
60
60
60
60
75
75
75
75
Address Setup Time
tAVWL
tAVEL
tAVSH
tAS
tAS
tAS
0
0
0
0
0
0
Address Valid to End of Write
tAVWH
tAW
60
75
Write Pulse Width
tWLWH
tWLEH
tWLSL
tWP
tWP
tWP
35
35
35
70
70
70
Write Recovery Time
tWHAX
tEHAX
tSLAX
tWR
tWR
tWR
5
5
5
5
5
5
Data Hold Time
tWHDX
tEHDX
tSLDX
tDH
tDH
tDH
0
0
0
0
0
0
Write to Output in High Z (1)
tWLQZ
tWHZ
0
30
0
35
Data to Write Time
tDVWH
tDVEH
tDVSL
tDW
tDW
tDW
35
35
35
40
40
40
Output Active from End of Write (1)
tWHQX
tWLZ
5
5
1. This parameter is guaranteed by design but not tested.
100ns
Min Max
100
85
85
85
85
0
0
0
85
80
80
80
5
5
5
0
0
0
0 40
40
40
40
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
4 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com



EDI88128C datasheet pdf
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