EBJ81UG8BAS0 Datasheet PDF - Elpida


www.Datasheet-PDF.com

EBJ81UG8BAS0
Elpida

Part Number EBJ81UG8BAS0
Description 8GB DDR3 SDRAM SO-DIMM
Page 16 Pages

EBJ81UG8BAS0 datasheet pdf
View PDF for PC
EBJ81UG8BAS0 pdf
View PDF for Mobile


No Preview Available !

PRELIMINARY DATA SHEET
8GB DDR3 SDRAM SO-DIMM
EBJ81UG8BAS0 (1024M words × 64 bits, 2 Ranks)
Specifications
Density: 8GB
Organization
1024M words × 64 bits, 2 ranks
Mounting 16 pieces of 4G bits DDR3 SDRAM sealed
in FBGA
Package: 204-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD = 1.5V ± 0.075V
Data rate: 1600Mbps/1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
Eight internal banks for concurrent operation
(components)
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS write latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1717E40 (Ver. 4.0)
Date Published January 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2010-2011



No Preview Available !

EBJ81UG8BAS0
Ordering Information
Part number
EBJ81UG8BAS0-GN-F
Data rate
Mbps (max.)
1600
EBJ81UG8BAS0-DJ-F 1333
Component
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
Package
204-pin SO-DIMM
(lead-free and
halogen-free)
Contact
pad
Gold
Mounted devices
EDJ4208BASE-GN-F
EDJ4208BASE-GN-F
EDJ4208BASE-DJ-F
Detailed Information
For detailed electrical specifications and further information, please refer to the component DDR3 SDRAM datasheet
EDJ4204BASE, EDJ4208BASE (E1705E).
Preliminary Data Sheet E1717E40 (Ver. 4.0)
2



No Preview Available !

EBJ81UG8BAS0
Pin Configurations
Front side
Pin
No. Pin name
1 VREFDQ
3 VSS
5 DQ0
7 DQ1
9 VSS
11 DM0
13 VSS
15 DQ2
17 DQ3
19 VSS
21 DQ8
23 DQ9
25 VSS
27 /DQS1
29 DQS1
31 VSS
33 DQ10
35 DQ11
37 VSS
39 DQ16
41 DQ17
43 VSS
45 /DQS2
47 DQS2
49 VSS
51 DQ18
53 DQ19
55 VSS
57 DQ24
59 DQ25
61 VSS
63 DM3
65 VSS
67 DQ26
69 DQ27
71 VSS
Back side
Pin
No. Pin name
2 VSS
4 DQ4
6 DQ5
8 VSS
10 /DQS0
12 DQS0
14 VSS
16 DQ6
18 DQ7
20 VSS
22 DQ12
24 DQ13
26 VSS
28 DM1
30 /RESET
32 VSS
34 DQ14
36 DQ15
38 VSS
40 DQ20
42 DQ21
44 VSS
46 DM2
48 VSS
50 DQ22
52 DQ23
54 VSS
56 DQ28
58 DQ29
60 VSS
62 /DQS3
64 DQS3
66 VSS
68 DQ30
70 DQ31
72 VSS
Front side
Back side
Pin Pin
No. Pin name No. Pin name
KEY
73 CKE0
74 CKE1
75 VDD
76 VDD
77 NC
78 A15
79 BA2
80 A14
81 VDD
82 VDD
83 A12(/BC) 84 A11
85 A9
86 A7
87 VDD
88 VDD
89 A8
90 A6
91 A5
92 A4
93 VDD
94 VDD
95 A3
96 A2
97 A1
98 A0
99 VDD
100 VDD
101 CK0
102 CK1
103 /CK0
104 /CK1
105 VDD
106 VDD
107 A10(AP) 108 BA1
109 BA0
110 /RAS
111 VDD
112 VDD
113 /WE
114 /CS0
115 /CAS
116 ODT0
117 VDD
118 VDD
119 A13
120 ODT1
121 /CS1
122 NC
123 VDD
124 VDD
125 NC
126 VREFCA
127 VSS
128 VSS
129 DQ32
130 DQ36
131 DQ33
132 DQ37
133 VSS
134 VSS
135 /DQS4
136 DM4
137 DQS4
138 VSS
139 VSS
140 DQ38
141 DQ34
142 DQ39
Front side
Pin
No. Pin name
143 DQ35
145 VSS
147 DQ40
149 DQ41
151 VSS
153 DM5
155 VSS
157 DQ42
159 DQ43
161 VSS
163 DQ48
165 DQ49
167 VSS
169 /DQS6
171 DQS6
173 VSS
175 DQ50
177 DQ51
179 VSS
181 DQ56
183 DQ57
185 VSS
187 DM7
189 VSS
191 DQ58
193 DQ59
195 VSS
197 SA0
199 VDDSPD
201 SA1
203 VTT
Back side
Pin
No. Pin name
144 VSS
146 DQ44
148 DQ45
150 VSS
152 /DQS5
154 DQS5
156 VSS
158 DQ46
160 DQ47
162 VSS
164 DQ52
166 DQ53
168 VSS
170 DM6
172 VSS
174 DQ54
176 DQ55
178 VSS
180 DQ60
182 DQ61
184 VSS
186 /DQS7
188 DQS7
190 VSS
192 DQ62
194 DQ63
196 VSS
198 NC
200 SDA
202 SCL
204 VTT
Preliminary Data Sheet E1717E40 (Ver. 4.0)
3



No Preview Available !

EBJ81UG8BAS0
Pin Description
Pin name
Function
A0 to A15
A10 (AP)
Address input
Row address
Column address
Auto precharge
A0 to A15
A0 to A9
A12 (/BC)
Burst chop
BA0, BA1, BA2
Bank select address
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0, CK1
Clock input
/CK0, /CK1
Differential clock input
ODT0, ODT1
ODT control
DQ0 to DQ63
Data input/output
DQS0 to DQS7, /DQS0 to /DQS7
Input and output data strobe
DM0 to DM7
Input mask
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0, SA1
Address input for serial PD
VDD*1
Power for internal circuit
VDDSPD
Power for serial PD
VREFCA
Reference voltage for CA
VREFDQ
Reference voltage for DQ
VSS
Ground
VTT I/O termination supply for SDRAM
/RESET
Set DRAM to a known state
NC No connection
Note: 1. The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Front side
1 pin 71 pin 73 pin
203 pin
2 pin 72 pin 74 pin
Back side
204 pin
Preliminary Data Sheet E1717E40 (Ver. 4.0)
4




EBJ81UG8BAS0 datasheet pdf
Download PDF
EBJ81UG8BAS0 pdf
View PDF for Mobile


Similiar Datasheets : EBJ81UG8BAS0

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Privacy Policy + Contact