CYBL10561 Datasheet PDF - Cypress Semiconductor


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CYBL10561
Cypress Semiconductor

Part Number CYBL10561
Description Programmable Radio-on-Chip
Page 30 Pages

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PRELIMINARY
CYBL10X6X Family Datasheet
Programmable Radio-on-Chip With
Bluetooth Low Energy (PRoC BLE)
General Description
PRoC BLE is a 32-bit, 48-MHz ARM® Cortex™-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width
modulators (TCPWM), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S. PRoC BLE includes a royalty-free
BLE stack compatible with Bluetooth® 4.1 and provides a complete, programmable, and flexible solution for HID, remote controls,
toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a simple, low-cost way to add BLE
connectivity to any system.
Features
Bluetooth® Smart Connectivity
Bluetooth 4.1 single-mode device
2.4-GHz BLE radio and baseband with integrated balun
TX output power: –18 dBm to +3 dBm
Received signal strength indicator (RSSI) with 1-dB resolution
RX sensitivity: –92 dBm
TX current: 15.6 mA at 0 dBm
RX current: 16.4 mA
ARM Cortex-M0 CPU Core
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
128-KB flash memory
16-KB SRAM memory
Emulated EEPROM using flash memory
Watchdog timer with dedicated internal low-speed oscillator
(ILO)
Ultra-Low-Power
1.3-µA Deep-Sleep mode with watch crystal oscillator (WCO)
on
150-nA Hibernate mode current with SRAM retention
60-nA Stop mode current with GPIO wakeup
CapSense® Touch Sensing with Two-Finger Gestures
Up to 36 capacitive sensors for buttons, sliders, and touchpads
Two-finger gestures: scroll, inertial scroll, pinch, stretch, and
edge-swipe
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
Automatic hardware-tuning algorithm (SmartSense™)
Peripherals
12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
Ultra-low-power LCD segment drive for 128 segments with
operation in Deep-Sleep mode
Two serial communication blocks (SCBs) supporting I2C
(Master/Slave), SPI (Master/Slave), or UART
Four dedicated 16-bit TCPWMs
Additional four 8-bit or two 16-bit PWMs
Programmable LVD from 1.8 V to 4.5 V
I2S Master interface
Clock, Reset, and Supply
Wide supply-voltage range: 1.9 V to 5.5 V
3-MHz to 48-MHz internal main oscillator (IMO) with 2%
accuracy
24-MHz external clock oscillator (ECO) without load capaci-
tance
32-kHz WCO
Programmable GPIOs
36 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z, or strong output
Any GPIO pin can be CapSense, LCD, or analog, with flexible
pin routing
Programming and Debug
2-pin SWD
In-system flash programming support
Temperature and Packaging
Operating temperature range: –40 °C to +85 °C
Available in 56-pin QFN (7 mm × 7 mm) and 68-ball WLCSP
(3.52 mm × 3.91 mm) packages
PSoC® Creator™ Design Environment
Easy-to-use IDE to configure, develop, program, and test a
BLE application
Option to export the design to Keil, IAR, or Eclipse
Bluetooth Low Energy Protocol Stack
Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or Broad-
caster roles
Switches between Central and Peripheral roles on-the-go
Standard Bluetooth Low Energy profiles and services for
interoperability
Custom profile and service for specific use cases
Errata: For information on silicon errata, see “Errata” on page 40. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90478 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 11, 2014



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PRELIMINARY
PRoC BLE: CYBL10X6X
Family Datasheet
Contents
Blocks and Functionality ................................................. 3
CPU Subsystem .......................................................... 4
BLE Subsystem........................................................... 4
System Resources Subsystem ................................... 4
Peripheral Blocks ........................................................ 5
Pinouts .............................................................................. 8
Power............................................................................... 13
Low-Power Modes ..................................................... 13
Development Support .................................................... 15
Documentation .......................................................... 15
Online ........................................................................ 15
Tools.......................................................................... 15
Kits ............................................................................ 15
Electrical Specifications ................................................ 16
Absolute Maximum Ratings....................................... 16
BLE Subsystem......................................................... 16
Device-Level Specifications ...................................... 19
Analog Peripherals .................................................... 24
Digital Peripherals ..................................................... 26
Memory ..................................................................... 29
System Resources .................................................... 29
Ordering Information...................................................... 33
Part Numbering Conventions .................................... 33
Packaging........................................................................ 35
Acronyms ........................................................................ 37
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Errata ............................................................................... 40
Errata Summary ........................................................ 40
Revision History ............................................................. 41
Sales, Solutions, and Legal Information ...................... 42
Worldwide Sales and Design Support....................... 42
Products .................................................................... 42
PSoC® Solutions ...................................................... 42
Cypress Developer Community................................. 42
Technical Support ..................................................... 42
Document Number: 001-90478 Rev. *F
Page 2 of 42



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PRELIMINARY
PRoC BLE: CYBL10X6X
Family Datasheet
Blocks and Functionality
The CYBL10X6X block diagram is shown in Figure 1. There are five major subsystems: CPU subsystem, BLE subsystem, system
resources, peripheral blocks, and I/O subsystem.
Figure 1. Block Diagram
The PRoC BLE family includes extensive support for
programming, testing, debugging, and tracing both hardware
and firmware. The complete debug-on-chip functionality enables
full-device debugging in the final system using the standard
production device. It does not require special interfaces,
debugging pods, simulators, or emulators. Only the standard
programming connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for PRoC BLE devices. The SWD interface
is fully compatible with industry-standard third-party tools.
PRoC BLE also supports disabling the SWD interface and has a
robust flash-protection feature.
Document Number: 001-90478 Rev. *F
Page 3 of 42



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PRELIMINARY
PRoC BLE: CYBL10X6X
Family Datasheet
CPU Subsystem
CPU
The CYBL10X6X device is based on an energy-efficient
ARM Cortex-M0 32-bit processor, offering low power
consumption, high performance, and reduced code size using
16-bit thumb instructions. The Cortex-M0’s ability to perform
single-cycle 32-bit arithmetic and logic operations, including
single-cycle 32-bit multiplication, helps in better performance.
The inclusion of the tightly-integrated Nested Vectored Interrupt
Controller (NVIC) with 32 interrupt lines enables the Cortex-M0
to achieve a low latency and a deterministic interrupt response.
The CPU also includes a 2-pin interface, the serial wire debug
(SWD), which is a 2-wire form of JTAG. The debug circuits are
enabled by default and can only be disabled in firmware. If
disabled, the only way to re-enable them is to erase the entire
device, clear flash protection, and reprogram the device with the
new firmware that enables debugging. In addition, it is possible
to use the debug pins as GPIO too. The device has four break-
points and two watchpoints for effective debugging.
Flash
The device has a 128-KB flash memory with a flash accelerator,
tightly coupled to the CPU to improve average access times from
flash. The flash is designed to deliver 1-wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access perfor-
mance on average. Part of the flash can be used to emulate
EEPROM operation, if required.
During flash erase and programming operations (the maximum
erase and program time is 20 ms per row), the IMO will be set to
48 MHz for the duration of the operation. This also applies to the
emulated EEPROM. System design must take this into account
because peripherals operating from different IMO frequencies
will be affected. If it is critical that peripherals continue to operate
with no change during flash programming, always set the IMO to
48 MHz and derive the peripheral clocks by dividing down from
this frequency.
SRAM
The low-power 16-KB SRAM memory retains its contents even
in Hibernate mode.
ROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
BLE Subsystem
The BLE subsystem consists of the link layer engine and
physical layer. The link layer engine supports both master and
slave roles. The link layer engine implements time-critical
functions such as encryption in the hardware to reduce the
power consumption, and provides minimal processor inter-
vention and a high performance. The key protocol elements,
such as host control interface (HCI) and link control, are imple-
mented in firmware. The direct test mode (DTM) is included to
test the radio performance using a standard Bluetooth tester.
The physical layer consists of a modem and an RF transceiver
that transmits and receives BLE packets at the rate of 1 Mbps
over the 2.4-GHz ISM band. In the transmit direction, this block
performs GFSK modulation and then converts the digital
baseband signal of these BLE packets into radio frequency
before transmitting them to air through an antenna. In the receive
direction, this block converts an RF signal from the antenna to a
digital bit stream after performing GFSK demodulation.
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-antenna terminal
through a pi-matching network. The output power is program-
mable from –18 dBm to +3 dBm to optimize the current
consumption for different applications.
The Bluetooth Low Energy protocol stack uses the BLE
subsystem and provides the following features:
Link Layer (LL)
Master and Slave roles
128-bit AES engine
Encryption
Low-duty-cycle advertising (Bluetooth 4.1 feature)
LE Ping (Bluetooth 4.1 feature)
Bluetooth Low Energy 4.1 single-mode protocol stack with
logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
Master and slave roles
API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
L2CAP connection-oriented channel (Bluetooth 4.1 feature)
GAP features
Broadcaster, Observer, Peripheral, and Central roles
Security mode 1: Level 1, 2, and 3
Security mode 2: Level 1 and 2
User-defined advertising data
Multiple-bond support
GATT features
GATT Client and Server
Supports GATT subprocedures
32-bit universally unique identifiers (UUID) (Bluetooth 4.1
feature)
Security Manager (SM)
Pairing methods: Just Works, Passkey Entry, and Out of
Band
Authenticated man-in-the-middle (MITM) protection and data
signing
Supports all SIG-adopted BLE profiles
System Resources Subsystem
Power
The power block includes internal LDOs that supply required
voltage levels for different blocks. The power system also
includes POR, BOD, and LVD circuits. The POR circuit holds the
device in the reset state until the power supplies have stabilized
at appropriate levels and the clock is ready. The BOD circuit
resets the device when the supply voltage is too low for proper
device operation. The LVD circuit generates an interrupt if the
supply voltage drops below a user-selectable level.
Document Number: 001-90478 Rev. *F
Page 4 of 42




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