CY62128DV30 Datasheet PDF - Cypress Semiconductor

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CY62128DV30
Cypress Semiconductor

Part Number CY62128DV30
Description 1-Mb (128K x 8) Static RAM
Page 11 Pages


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CY62128DV30
1-Mb (128K x 8) Static RAM
Features
• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
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— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 32-lead SOIC,
32-lead TSOP and 32-lead Small TSOP, non Pb-free
32-lead Reverse TSOP packages
Functional Description[1]
The CY62128DV30 is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life(MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The
input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when: deselected Chip Enable 1 (CE1)
HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE
HIGH), or during a write operation (Chip Enable 1 (CE1) LOW
and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable
(WE) LOW. Data on the eight I/O pins is then written into the
location specified on the Address pin (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O
pins.
The eight input/output pins (I/Oo through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or
during a write operation (CE1 LOW, CE2 HIGH), and WE
LOW).
A0
A1
A2
A3
A4
A5
A6
A7
AAA1089
A11
CE1
CE2
WE
OE
Data in Drivers
128K x 8
ARRAY
COLUMN
DECODER
Power-
down
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05231 Rev. *H
Revised June 19, 2006



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Pin Configurations[2]
CY62128DV30
Top View
SOIC
DNU
A16
A14
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A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A11
A9
A8
A13
WE
CE2
A15
VCC
DNU
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32 OE
A11
31 A10
A9
30 CE1
A8
29 I/O7 A13
28 I/O6 WE
27 I/O5 CE2
26 I/O4 A15
25
24
I/O3 VCC
GND DNU
23 I/O2 A16
22
21
I/O1
I/O0
A14
A12
20 A0
A7
19 A1
18 A2
17 A3
A6
A5
A4
25
26
226 7
28
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
16 GND
15 I/O2
14 I/O1
13 I/O0
12 A0
11 A1
10 A2
9 A3
A4
A5
A6
A7
A12
A14
A16
DNU
VCC
A15
CE2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reverse TSOP I
Top View
(not to scale)
17 A3
18 A2
19 A1
20 A0
21 I/O0
22 I/O1
23 I/O2
24 GND
25 I/O3
26 I/O4
27 I/O5
28 I/O6
29 I/O7
30 CE1
31 A10
32 OE
Product Portfolio
Product
CY62128DV30L
CY62128DV30LL
VCC Range (V)
Min.
Typ.
Max.
2.2 3.0 3.6
Speed
(ns)
55/70
55/70
Power Dissipation
Operating, ICC (mA)
f = 1 MHz
Typ.[4] Max.
f = fMAX
Typ.[4] Max.
Standby, ISB2 (µA)
Typ.[4] Max.
0.85 1.5
5
10 1.5
5
0.85 1.5 5 10 1.5 4
Notes:
2. NC pins are not connected to the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05231 Rev. *H
Page 2 of 11



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CY62128DV30
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground
Potential .......................................................... 0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................0.3V to VCC + 0.3V
DC Input Voltage[5] ................................ 0.3V to VCC + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature (TA)
40°C to +85°C
VCC[6]
2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
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Parameter
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
ISB1
ISB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
VCC Operating Supply
Current
Automatic CE Power-down
Current CMOS Inputs
Automatic CE Power-down
Current CMOS Inputs
Test Conditions
2.2 < VCC < 2.7
IOH = 0.1 mA
2.7 < VCC < 3.6
IOH = 1.0 mA
2.2 < VCC < 2.7
IOL = 0.1 mA
2.7 < VCC < 3.6
IOL = 2.1 mA
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
GND < VI < VCC
GND < VO < VCC, Output Disabled
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V,
IOUT = 0mA,
CMOS level
CE1 > VCC 0.2V, CE2 < 0.2V, L
VIN > VCC 0.2V, VIN < 0.2V,
f = fMAX (Address and Data Only),
LL
f = 0 (OE, WE,)
CE1 > VCC 0.2V, CE2 < 0.2V,
VIN > VCC 0.2V or VIN < 0.2V,
f = 0, VCC=3.6V
L
LL
CY62128DV30-55/70
Min.
Typ.[4]
Max.
2.0
2.4
0.4
0.4
1.8
2.2
0.3
VCC + 0.3
VCC + 0.3
0.6
0.3 0.8
1 +1
1 +1
5 10
0.85 1.5
Unit
V
V
V
V
µA
µA
mA
1.5 5 µA
1.5 4
1.5 5 µA
1.5 4
Capacitance[7]
CIN
COUT
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[7]
Parameter
Description
Test Conditions
SOIC TSOP I RTSOP STSOP Unit
θJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 69
inch, two-layer printed circuit
93
θJC Thermal Resistance (Junction to Case) board
34 17
Notes:
5. VIL(min.) = 2.0V for pulse durations less than 20 ns. VIH(max.) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device operation requires linear ramp of VCC from 0V to VCC(min) and VCC must be stable at VCC(min) for 500 µ s.
7. Tested initially and after any design or process changes that may affect these parameters.
93
17
65 °C/W
15 °C/W
Document #: 38-05231 Rev. *H
Page 3 of 11



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CY62128DV30
AC Test Loads and Waveforms[8]
R1
VCC ALL INPUT PULSES
OUTPUT
50 pF
VCC 10% 90%
R2 GND
Rise Time = 1 V/ns
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
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Parameters
R1
R2
RTH
VTH
2.5V (2.2V - 2.7V)
16600
15400
8000
1.20
3.0V (2.7V - 3.6V)
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
Parameter
Description
Conditions
VDR
ICCDR
tCDR[4]
tR[8]
VCC for Data Retention
Data Retention Current
VCC = 1.5V, CE1 > VCC 0.2V, CE2 < 0.2V, L
VIN > VCC 0.2V or VIN < 0.2V
LL
Chip Deselect to Data Retention Time
Operation Recovery Time
Min.
1.5
0
100
Typ.[4] Max. Unit
V
4 µA
3
ns
µs
Data Retention Waveform
VCC
CE1
or
CE2
V CC(min.)
tCDR
DATA RETENTION MODE
VDR > 1.5V
VCC(min.)
tR
Note:
8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs.
Document #: 38-05231 Rev. *H
Page 4 of 11



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CY62128DV30 1-Mb (128K x 8) Static RAM CY62128DV30
Cypress Semiconductor
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