CY62128DV30 Datasheet PDF - Cypress Semiconductor

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CY62128DV30
Cypress Semiconductor

Part Number CY62128DV30
Description 1-Mb (128K x 8) Static RAM
Page 11 Pages


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CY62128DV30
1-Mb (128K x 8) Static RAM
Features
• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
www.DataSheet4U.com
— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 32-lead SOIC,
32-lead TSOP and 32-lead Small TSOP, non Pb-free
32-lead Reverse TSOP packages
Functional Description[1]
The CY62128DV30 is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life(MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The
input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when: deselected Chip Enable 1 (CE1)
HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE
HIGH), or during a write operation (Chip Enable 1 (CE1) LOW
and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable
(WE) LOW. Data on the eight I/O pins is then written into the
location specified on the Address pin (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O
pins.
The eight input/output pins (I/Oo through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or
during a write operation (CE1 LOW, CE2 HIGH), and WE
LOW).
A0
A1
A2
A3
A4
A5
A6
A7
AAA1089
A11
CE1
CE2
WE
OE
Data in Drivers
128K x 8
ARRAY
COLUMN
DECODER
Power-
down
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05231 Rev. *H
Revised June 19, 2006

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Cypress Semiconductor
CY62128DV30 pdf

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