CY2PP3210 Datasheet PDF - Cypress Semiconductor

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CY2PP3210
Cypress Semiconductor

Part Number CY2PP3210
Description Dual 1:5 Differential Clock / Data Fanout Buffer
Page 9 Pages


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FastEdge™ Series
CY2PP3210
Dual 1:5 Differential Clock/Data Fanout Buffer
Features
• Dual sets of five ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 0.8 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.2 GHz max. toggle frequency)
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6210
Functional Description
The CY2PP3210 is a low-skew, low propagation delay dual
1-to-5 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3210 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout distributing a single-ended signal. An external bias pin,
VBB, is provided for this purpose. In such an application, the
VBB pin should be connected to either one of the CLKA# or
CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.
Traditionally, in ECL, it is used to provide the reference level
to a receiving single-ended input that might have a differential
bias point.
Since the CY2PP3210 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3210 delivers consistent performance
over various platforms.
Block Diagram
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
VEE
QA0
QA0#
QA1
QA1#
QA2
QA2#
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
QB2
QB2#
QB3
QB3#
QB4
QB4#
VBB
Pin Configuration
VCC 1
24 QA3
NC 2
23 QA3#
CLKA 3
22 QA4
CLKA#
VBB
4
5
CY2PP3210
21 QA4#
20 QB0
CLKB 6
19 QB0#
CLKB# 7
18 QB1
VEE 8
17 QB1#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07508 Rev.*C
Revised July 28, 2004



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FastEdge™ Series
CY2PP3210
Pin Definitions[1, 2, 3]
Pin
Name I/O[1]
Type
Description
2 NC No connect.
3 CLKA, I,PD ECL/PECL ECL/PECL Differential Input Clocks.
4 CLKA# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
5
VBB[3]
O
Bias Reference Voltage Output.
6 CLKB, I,PD ECL/PECL ECL/PECL Differential Input Clocks.
7 CLKB# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
8
VEE[2] –PWR
Power Negative Supply.
1,9,16,25,32
VCC +PWR Power Positive Supply.
31,29,27,24,22
QA(0:4) O ECL/PECL True output
30,28,26,23,21
QA#(0:4) O ECL/PECL Complement output
20,18,15,13,11
QB(0:4) O ECL/PECL True output
19,17,14,12,10
QB#(0:4) O ECL/PECL Complement output
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3210. The agency name and relevant specification is
listed below in Table 2.
Table 1.
Agency Name
Specification
JEDEC
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2.
IaVnnEdEE CaisrLecmobnoendtweece(tenenedgVtaoCtiCGveNanpDdo(wV0eVErE) .saunpdpVlyCmC oisdee)it,hVeErE+i3s.3eVithoerr+–23..53VV.
or
In
b–o2t.h5VmaonddesV, CthCeisincpountnaencdteoduttopuGt NleDve(l0sVa)r.eInrePfeErCenLcmedodtoe
(positive
the most
power supply mode),
positive supply (VCC)
3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Document #: 38-07508 Rev.*C
Page 2 of 9



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FastEdge™ Series
CY2PP3210
Absolute Maximum Ratings
Parameter
Description
Condition
Min.
Max.
VCC
VEE
TS
TJ
ESDh
MSL
Gate Count
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
Moisture Sensitivity Level
Total Number of Used Gates
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
Assembled Die
–0.3 4.6
-4.6 0.3
–65 +150
150
2000
3
50
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Unit
V
V
°C
°C
V
N.A.
gates
Operating Conditions
Parameter
Description
IBB
LUI
TA
ØJc
ØJa
IEE
CIN
LIN
VIN
VTT
VOUT
IIN
Output Reference Current
Latch Up Immunity
Temperature, Operating Ambient
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Maximum Quiescent Supply Current
Input pin capacitance
Pin Inductance
Input Voltage
Output Termination Voltage
Output Voltage
Input Current[7]
Condition
Relative to VBB
Functional, typical
Functional
Functional
Functional
VEE pin[5]
Relative to VCC[6]
Relative to VCC[6]
Relative to VCC[6]
VIN = VIL, or VIN = VIH
Min.
–40
–0.3
–0.3
Max.
|200|
100
29[4]
76[4]
+85
130
3
1
VCC + 0.3
VCC – 2
VCC + 0.3
l150l
Unit
uA
mA
°C
°C/W
°C/W
mA
pF
nH
V
V
V
uA
PECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
VCC
VCMR
VOH
VOL
VIH
VIL
VBB[3]
Operating Voltage
Differential Cross Point Voltage[8]
Output High Voltage
Output Low Voltage
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
2.5V ± 5%, VEE = 0.0V
3.3V ± 5%, VEE = 0.0V
Differential operation
IOH = –30 mA[9]
IOL = –5 mA[9]
Single-ended operation
Single-ended operation
Relative to VCC[6]
2.375
3.135
1.2
VCC – 1.25
2.625
3.465
VCC
VCC – 0.7
VCC – 1.995
VCC –1.995
VCC – 1.5
VCC – 1.3
VCC – 1.165 VCC – 0.880 [10]
VCC – 1.945 [10] VCC – 1.625
VCC – 1.620 VCC – 1.220
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip.
6. where VCC is 3.3V±5% or 2.5V±5%
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9. Equivalent to a termination of 50to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50;
10. VIL will operate down to VEE; VIH will operate up to VCC
Unit
V
V
V
V
V
V
V
V
V
Document #: 38-07508 Rev.*C
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FastEdge™ Series
CY2PP3210
ECL DC Electrical Specifications
Parameter
Description
VEE Negative Power Supply
VCMR
VOH
VOL
VIH
VIL
VBB[3]
Differential cross point voltage[8]
Output High Voltage
Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Condition
–2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
Differential operation
IOH = –30 mA[9]
IOL = –5 mA[9]
Single-ended operation
Single-ended operation
Min.
–2.625
–3.465
VEE + 1.2
–1.25
–1.995
–1.995
–1.165
–1.945 [10]
– 1.620
Max.
–2.375
–3.135
0V
–0.7
–1.5
–1.3
–0.880 [10]
–1.625
– 1.220
Unit
V
V
V
V
V
V
V
AC Electrical Specifications
Parameter
Description
VPP Differential Input Voltage[8]
FCLK
Input Frequency
TPD Propagation Delay CLKA or CLKB to
Output pair
Vo Output Voltage (peak-to-peak; see
Figure 2)
VCMRO
tsk(0)
tsk(PP)
TPER
tsk(P)
Output Common Voltage Range (typ.)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (rms)[12]
Output Pulse Skew[13]
Condition
Differential operation
50% duty cycle Standard load
660 MHz [11]
< 1 GHz
660 MHz [11], See Figure 3
660 MHz [11]
660 MHz [11]
660 MHz [11], See Figure 3
Min.
0.1
280
Max.
1.3
1.5
750
0.375
VCC – 1.425
– 50
– 150
– 0.8
– 50
TR,TF
Output Rise/Fall Time (see Figure 2) 660 MHz 50% duty cycle
0.08
0.3
Differential 20% to 80%
Timing Definitions
VCC
VCMR Max = VCC
VIH
Unit
V
GHz
ps
V
V
ps
ps
ps
ps
ns
VPP
VPP range
0.1V - 1.3V
VCMR
VIL
VCMR Min = VEE + 1.2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
Notes:
11. 50% duty cycle; standard load; differential operation
12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
Document #: 38-07508 Rev.*C
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Cypress Semiconductor
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