CY2DP3110 Datasheet PDF - Cypress Semiconductor

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CY2DP3110
Cypress Semiconductor

Part Number CY2DP3110
Description Differential Clock/Data Fanout Buffer
Page 9 Pages


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FastEdge™ Series
CY2DP3110
1 of 2:10 Differential Clock/Data Fanout Buffer
Features
• Ten ECL/PECL differential outputs
• One ECL/PECL differential or single-ended inputs
(CLKA)
• One HSTL differential or single-ended inputs (CLKB)
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 400 ps propagation delay (typical)
• 1.2 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.7 GHz maximum toggle
frequency)
• PECL and HSTL mode supply range: VCC = 2.5V± 5% to
3.3V±5% with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin TQFP package
• Temperature compensation like 100K ECL
• Pin-compatible with MC100ES6111
Functional Description
The CY2DP3110 is a low-skew, low propagation delay 2-to-10
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3110 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on HSTL
single-ended signal to 10 ECL/PECL differential loads. An ex-
ternal bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-µF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.
Since the CY2DP3110 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in com-
munication systems. Furthermore, advanced circuit design
schemes, such as internal temperature compensation, ensure
that the CY2DP3110 delivers consistent performance over
various platforms
Block Diagram
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
CLK_SEL
VEE
VEE
VBB
VBB
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Pin Configuration
VCC 1
24 Q3
CLK_SEL 2
23 Q3#
CLKA 3
22 Q4
CLKA#
VBB
4
5
CY2DP3110
21
20
Q4#
Q5
CLKB 6
19 Q5#
CLKB# 7
18 Q6
VEE 8
17 Q6#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07469 Rev.*G
Revised July 28, 2004



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FastEdge™ Series
CY2DP3110
Pin Definitions[1, 2, 3]
Pin
2
3
4
Name
I/O
CLK_SEL I,PD
CLKA I,PD[1]
CLKA# I,PD/PU
Type
ECL/PECL
ECL/PECL
ECL/PECL
Description
Input Clock Select.
Differential Input Clocks.
Differential Input Clocks.
5
6
7
8
1,9,16,
25,32
31,29,27,24,22,20,18,
15,13,11
30,28,26,23,21,19,17,
14,12,10
VBB
CLKB,
CLKB#
VEE
VCC
O
I,PD
I,PD/PU
–PWR
+PWR
Bias
HSTL
HSTL
Power
Power
Reference Voltage Output.
Alternate Differential Input Clocks.
Alternate Differential Input Clocks.
Negative Power Supply.
Positive Power Supply.
Q(0:9)
O ECL/PECL ECL/PECL Differential Output Clocks.
Q#(0:9) O ECL/PECL ECL/PECL Differential Output Clocks.
Table 1.
Control
CLK_SEL
0
1
Operation
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL compatible signals with respective power configurations
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3110. The agency name and relevant specification is
listed below in Table 2.
Table 2.
Agency Name
Specification
JEDEC
JESD 020B (MSL)
JESD 8-6 (HSTL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2.
IaVnnEdEE CaisrLecmobnoendtweece(tenenedgVtaoCtiCGveNanpDdo(wV0eVErE) .saunpdpVlyCmC oisdee)it,hVeErE+i3s.3eVithoerr+–23..53VV.
or
In
b–o2t.h5VmaonddesV, CthCeisincpountnaencdteoduttopuGt NleDve(l0sVa)r.eInrePfeErCenLcmedodtoe
(positive
the most
power supply mode),
positive supply (VCC)
3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Document #: 38-07469 Rev.*G
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FastEdge™ Series
CY2DP3110
Absolute Maximum Ratings
Parameter
Description
Condition
Min.
Max.
VCC
VEE
TS
TJ
ESDh
MSL
Gate Count
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
Moisture Sensitivity Level
Total Number of Used Gates
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
Assembled Die
–0.3 4.6
-4.6 0.3
–65 +150
150
2000
3
50
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
Description
IBB Output Reference Current
LUI Latch Up Immunity
TA Temperature, Operating Ambient
ØJc Dissipation, Junction to Case
ØJa Dissipation, Junction to Ambient
IEE Maximum Quiescent Supply Current
Condition
Relative to VBB
Functional, typical
Functional
Functional
Functional
VEE pin
Min.
–40
100
35[4]
76[4]
Max.
|200|
+85
130[5]
Unit
V
V
°C
°C
V
N.A.
gates
Unit
uA
mA
°C
°C/W
°C/W
mA
CIN
LIN
VIN
VTT
VOUT
IIN
Input pin capacitance
Pin Inductance
Input Voltage
Output Termination Voltage
Output Voltage
Input Current[7]
Relative to VCC[6]
Relative to VCC[6]
Relative to VCC[6]
VIN = VIL, or VIN = VIH
PECL/HSTL DC Electrical Specifications
–0.3
–0.3
3
1
VCC + 0.3
VCC – 2
VCC + 0.3
l150l
pF
nH
V
V
V
uA
Parameter
Description
Condition
Min.
Max.
Unit
VCC
VCMR
Operating Voltage
PECL Input Differential Cross Point
Voltage[8]
2.5V ± 5%, VEE = 0.0V
3.3V ± 5%, VEE = 0.0V
Differential operation
2.375
3.135
1.2
2.625
3.465
VCC
V
V
V
VX
HSTL Input Differential Crosspoint Volt- Standard Load Differential
age[9]
Operation
0.68
0.9 V
VOH
VOL
VIH
VIL
VBB[3]
Output High Voltage
Output Low Voltage
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
IOH = –30 mA[10]
IOL = –5 mA[10]
Single-ended operation
Single-ended operation
Relative to VCC[6]
VCC – 1.25
VCC – 0.7
VCC – 1.995
VCC –1.995
VCC – 1.5
VCC – 1.3
VCC – 1.165 VCC – 0.880 [11]
VCC – 1.945 [11] VCC – 1.625
VCC – 1.620 VCC – 1.220
V
V
V
V
V
V
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip.
6. where VCC is 3.3V±5% or 2.5V±5%
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9.
sVwX(inAgCl)ieiss
the crosspoint of the differential HSTL input signal. Normal AC operation is obtained
within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device
wprhoepnagthaetiocnrodsesplaoyi,ndt eisviwceithainndthpeaVrt-Xt(oA-pCa)rrtasnkgeew.aRndeftehretoinFpiugt.
2.
10. Equivalent to a termination of 50to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50;
11. VIL will operate down to VEE; VIH will operate up to VCC
Document #: 38-07469 Rev.*G
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FastEdge™ Series
CY2DP3110
ECL DC Electrical Specifications
Parameter
Description
VEE Negative Power Supply
VCMR
VOH
VOL
VIH
VIL
VBB[3]
ECL Input Differential cross point
voltage[8]
Output High Voltage
Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Condition
–2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
Differential operation
IOH = –30 mA[10]
IOL = –5 mA[10]
Single-ended operation
Single-ended operation
Min.
–2.625
–3.465
VEE + 1.2
–1.25
–1.995
–1.995
–1.165
–1.945 [11]
– 1.620
Max.
–2.375
–3.135
0V
–0.7
–1.5
–1.3
–0.880 [11]
–1.625
– 1.220
Unit
V
V
V
V
V
V
V
AC Electrical Specifications
Parameter
Description
VPP PECL/ECL Differential Input Voltage[8]
VCMRO
Output Common Voltage Range (typ.)
FCLK
Input Frequency
TPD
Propagation Delay CLKA or CLKB to
Output pair[13]
VDIF
HSTL Differential Input Voltage[12]
Vo
tsk(0)
tsk(PP)
TPER
tsk(P)
Output Voltage (peak-to-peak; see
Figure 2)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (rms)[14]
Output Pulse Skew[15]
Condition
Differential operation
50% duty cycle Standard load
PECL, ECL = 660 MHz
HSTL < 1GHz
Duty Cycle Standard Load
Differential Operation
< 1 GHz
660 MHz [13], See Figure 3
660 MHz [13]
660 MHz [13]
660 MHz [13], See Figure 3
Min.
Max.
0.1 1.3
VCC – 1.425
– 1.5
280 650
280 750
0.4 1.9
0.375
– 50
– 150
– 1.2
– 50
Unit
V
V
GHz
ps
ps
V
V
ps
ps
ps
ps
TR,TF
Output Rise/Fall Time (see Figure 2) 660 MHz 50% duty cycle
0.08
0.3 ns
Differential 20% to 80%
Notes:
12. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew
13. 50% duty cycle; standard load; differential operation
14. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points.
15. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
Document #: 38-07469 Rev.*G
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