CXD2951GA-4 Datasheet PDF - Sony Corporation


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CXD2951GA-4
Sony Corporation

Part Number CXD2951GA-4
Description Single Chip GPS LSI
Page 26 Pages

CXD2951GA-4 datasheet pdf
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Single Chip GPS LSI
CXD2951GA-4
Description
The CXD2951GA-4 is a dedicated single chip LSI
for the GPS (Global Positioning System), satellite-
based location measurement system. This LSI
enables the configuration of a single chip system
providing a cost-effective, low-power solution.
Compared with conventional methods, position
detection time and sensitivity are substantially
improved with the use of an advanced signal
processing scheme. With the integration of both the
Radio and baseband blocks into a single CMOS IC,
the CXD2951GA-4 is ideal for use in automotive,
cellular handset, handheld navigation, mobile
computing and other location-based applications.
Features
WAAS support
12-channel GPS receiver capable of simultaneously
receiving 12 satellites
Reception frequency: 1575.42MHz
(L1 band, CA code)
Reference clock (TCXO) frequency:
18.414MHz (GPS, Sony standard),
The unique frequency of major applications is available,
such as GSM and W-CDMA. (optional)
13.000MHz (GSM),
14.400MHz (CDMA),
16.368MHz (GPS),
19.800MHz (PDC/CDMA),
26.000MHz (GSM)
32 bits RISC CPU (ARM7TDMI)
288K-bytes Program ROM
72K-bytes Data RAM
Power is supplied only to 8K-byte Data RAM while
in backup mode.
System power management
1-channel UART
Internal RTC (Real Time Clock)
10-bit successive approximation system A/D
converter
All-in-view positioning
Communication format: Supports NMEA-0183 (Ver
3.01)
1 PPS output
176 pin LFLGA (Plastic)
Radio
Image Rejection Mixer
VCO Tank
IF Filters
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage I/O IOVDD
Supply voltage core CVDD
Supply voltage radio VDD
Input voltage
VI
Output voltage
VO
Operating temperature Topr
Storage temperature Tstg
–0.5 to +4.6
–0.5 to +2.5
–0.5 to +2.5
–0.5 to +6
–0.5 to +6
–40 to +85
–50 to +150
V
V
V
V
V
°C
°C
Recommended Operating Conditions
Supply voltage I/O IOVDD 3.0 to 3.6
V
Under operation with internal ROM, using no
external expansion bus:
IOVDD 2.6 to 3.6
Under operation in backup mode:
V
BKUPIOVDD 2.5 (Min.) V
Supply voltage core CVDD 1.62 to 1.98 V
Supply voltage radio VDD 1.62 to 1.98 V
Operating temperature Topr –40 to +85 °C
Input/Output Pin Capacitance (Baseband)
Input capacitance
CIN
9 (Max.)
Output capacitance COUT 11 (Max.)
I/O capacitance
CI/O 11 (Max.)
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04Z13



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CXD2951GA-4
Performance
Baseband
Tracking sensitivity: –152dBm (average) or less
Acquisition sensitivity: –139dBm (average) or less in Normal mode
Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier
with NF 2dB, 25dB gain.
TTFF (Time to First Fix):
Time until initial position measurement after power-on with the following conditions:
Cold Start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility)
Warm Start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility)
Hot Start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility)
Reference data with elevation angle of 5° or more and no interception environment with satellite powers
–130dBm.
Note) "95% possibility" means "position time with 95% possibility".
Positioning accuracy:
2DRMS: approx. 2m
Reference data with elevation angle of 5° or more and no interception environment with satellite powers
–130dBm.
Measurement data update time: 1s
Power consumption:
50mW (average) while position calculating with tracking satellites in low power mode
120mW (average) while position calculating with acquiring and tracking satellites
Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its
amplitude is 3.3V swing.
1PPS output
1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97).
Note) These values are not guaranteed, depending on the conditions.
Radio
Total Gain (typ.):
100dB
Noise figure (typ.):
8dB
Synthesizer phase noise (typ.):
–70dBc/Hz (10kHz)
–80dBc/Hz (100kHz)
PLL spurious (typ.):
–45dBc (inside fosc ±1.023MHz)
–55dBc (outside fosc ±1.023MHz)
Note) These values are not guaranteed.
–2–



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System Block Diagram
CXD2951GA-4
1575.42MHz
LNA
TCXO
CPU
Freq.
Synthesizer
RF/IF
1575.42MHz 1.023MHz
BPF
SAW
TCXO
Reference clock
18.414MHz
(GPS, Sony standard)
LNA
Down
Converter
1.023MHz
LPF
1 bit
Acquisition Block
Acquire GPS signals
Tracking Block
Locking to GPS signals
12ch correlations
Costas Loop & DLL
Computation
& Control
Control Acquisition
& Tracking block
Position calculating
ARM7TDMI
RTC
Timer
3ch
RAM
72KB
ROM
288KB
I/O
UART
A/D
X'tal
32.768kHz
–3–



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Pin Configuration (Top View)
CXD2951GA-4
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
V 87 85 81 79 76 75 71 67 64 62 59 57 53 50 49 47
EA3 EA5 CVSS3 EA9 IOVDD2 IOVSS2 EA15 EA19 ETEST0 CVSS2 IF2GND IF1GND TEST MIXGND LNASRC RFIN
OUTP
U 90 88 86 83 80 77 73 70 68 63 60 56 54 48 46 45 44 42
EA0 EA2
EA4 EA7
EA8 EA11 EA13 EA16 EA18 CVDD2 VCOM IF1VCC TEST MIXGND MIXGND LNASRC MIXGND NRING
OUTN
T 92 89 84 82 78 74 72 69 66 65 61 58 52 55 51 40 43 41
CVDD4 EA1
EA6 CVDD3 EA10 EA12 EA14 EA17 ETEST2 ETEST1 RREF IF2VCC TESTINN TEST TESTINP RFSUB RFRREF LNAMAT
OUTD
R 93 91 96
37 39 38
ECLKI CVSS4 IOVDD3
P 94 95 98
VDDVCO VCODE VSSVCO
CAP
33 35 36
ECLKO IOVSS3 EXROMI
VDDCP LPFRF VSSCP
N 102 97 100
EADVRB ECLKOUT EAVDPLL
31 32 34
VDDPLL VSSPLL LPFIF
M 104 99 103
EVIN1 EAVSPLL EVIN0
27 28 30
ETESTTCK TMS RADIOSUB
L 106 101 105
EVIN3 EAVSAD EVIN2
29 24
ETESTTMS TDI
26
TCK
K 110 108 107
ETEST3 EAVDAD EADVRT
25 21 22
ETESTTDI ETESTTINT TDO
J 112 109 111
IOVDD7 IOVSS8 ETEST4
23 19 18
ETESTTDO CVDD1 CVSS1
H 115 114 113
ECCKI BKUPCVDD BKUPCVSS
20 15 17
TRST IOVDD1 EXTCXO
G 116 117 119
ECCKO BKUPIOVSS EOSCEN
13 12 16
EPORT12 EPORT11 ETCXO
F 118 121 122
BKUPIOVDD ECLKS1 ECLKS2
11 9 14
EPORT10 EPORT8 IOVSS1
E 120 123 125
ECLKS0 IOVSS4 EXCS1
7 6 10
EPORT6 EPORT5 EPORT9
D 126 124 127
EXOE EXCS0 EXWE3
538
EPORT4 EPORT2 EPORT7
C 128 131 129 137 139 143 145 147 155 158 161 165 167 169 173 1 176 4
EXWE2 IOVSS5 EXWE1 ED27 ED25 ED21 ED19 ED17 ED15 ED12 ED9 ED5 ED3 ED1 ERXD0 EPORT0 IOVDD6 EPORT3
B
130 132 133 135 138 141 146 149 150 154 157 159 163 164 171 175 174
2
EXWE0 IOVDD4 ED31 ED29 ED26 ED23 ED18 CVSS5 CVDD5 IOVDD5 ED13 ED11 ED7 ED6 CVSS6 IOVSS7 ETXD0 EPORT1
A 134 136 140 142 144 148 151 152 153 156 160 162 166 168 170 172
ED30 ED28 ED24 ED22 ED20 ED16 EXRS ETESTXRS IOVSS6 ED14 ED10 ED8 ED4 ED2 ED0 CVDD6
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
: Pin 1 index.
–4–




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