CS42L51 Datasheet PDF - Cirrus Logic


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CS42L51
Cirrus Logic

Part Number CS42L51
Description Stereo CODEC
Page 30 Pages

CS42L51 datasheet pdf
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CS42L51
Low-Power, Stereo Codec with Headphone Amp
DIGITAL-TO-ANALOG FEATURES
98-dB dynamic range (A-weighted)
-86-dB THD+N
Headphone amplifier - GND centered
– On-chip charge pump provides –VA_HP
– No DC-blocking capacitor required
– 46-mW power into stereo 16 @ 1.8 V
– 88-mW power into stereo 16 @ 2.5 V
– -75 dB THD+N
Digital signal processing engine
– Bass & treble tone control, de-emphasis
– PCM + ADC mix with independent volume
control
– Master digital volume control
– Soft ramp & zero-cross transitions
Beep generator
– Tone selections across two octaves
– Separate volume control
– Programmable on & off time intervals
– Continuous, periodic or one-shot beep
selections
Programmable peak-detect and limiter
Pop and click suppression
ANALOG-TO-DIGITAL FEATURES
98-dB dynamic range (A-weighted)
-88-dB THD+N
Analog gain controls
– +32-dB or +16-dB mic preamplifiers
– Analog programmable gain amplifier (PGA)
+20-dB digital boost
Programmable automatic level control (ALC)
– Noise gate for noise suppression
– Programmable threshold and
attack/release rates
Independent channel control
Digital volume control
High-pass filter disable for DC measurements
Stereo 3:1 analog input MUX
Dual mic inputs
– Programmable, low noise mic bias levels
– Differential mic mix for common mode
noise rejection
Very low 64 Fs oversampling clock reduces
power consumption
1.8 V to 3.3 V
1.8 V to 2.5 V
1.8 V to 2.5 V
1.8 V to 2.5 V
Serial Audio 
Input
Hardware Mode 
or I2C & SPI 
Software Mode
Control Data
Reset
Serial Audio 
Output
Beep 
Generator
High Pass 
Filters
Register 
Configuration
Digital 
Signal 
Processing
Engine
MUX Switched 
Capacitor DAC 
Multibit
and Filter
Modulator
Switched 
Capacitor DAC 
MUX and Filter
ALC
Multibit
Oversampling  MUX PGA
Volume 
ADC
Controls
Multibit
Oversampling  MUX PGA
ADC
ALC
Headphone
Amp ‐ GND 
Centered
Headphone
Amp ‐ GND 
Centered
Charge 
Pump
MUX
+32 dB
+32 dB
MIC
Bias
Left HP Out
Right HP Out
Stereo Input 1
Stereo Input 2
Stereo Input 3 / 
Mic Input 1 & 2
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2005–2015
(All Rights Reserved)
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CS42L51
SYSTEM FEATURES
24-bit converters
4–96-kHz sample rate
Multibit delta–sigma architecture
Low power operation
– Stereo playback: 12.93 mW @ 1.8 V
– Stereo record and playback: 20.18 mW @
1.8 V
Variable power supplies
– 1.8–2.5 V digital & analog
– 1.8–3.3 V interface logic
Power down management
– ADC, DAC, codec, mic preamplifier, PGA
Software Mode (I²Cand SPIcontrol)
Hardware mode (stand-alone control)
Digital routing/mixes:
– Analog out = ADC + Digital In
– Digital out = ADC + Digital In
– Internal digital loopback
– Mono mixes
Flexible clocking options
– Master or slave operation
– High-impedance digital output option (for
easy MUXing between the codec and other
data sources)
– Quarter-speed mode (i.e., Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
APPLICATIONS
HDD and flash-based portable audio players
MD players/recorders
PDAs
Personal media players
Portable game consoles
Digital voice recorders
Digital camcorders
Digital cameras
Smart phones
GENERAL DESCRIPTION
The CS42L51 is a highly integrated, 24-bit, 96-kHz, low
power stereo codec. Based on multi-bit, delta-sigma
modulation, it allows infinite sample rate adjustment be-
tween 4 kHz and 96 kHz. Both the ADC and DAC offer
many features suitable for low power, portable system
applications.
The ADC input path allows independent channel control
of a number of features. An input multiplexer selects be-
tween line-level or microphone level inputs for each
channel. The microphone input path includes a select-
able programmable-gain pre-amplifier stage and a low
noise MIC bias voltage supply. A PGA is available for
line or microphone inputs and provides analog gain with
soft ramp and zero-cross transitions. The ADC also fea-
tures a digital volume attenuator with soft ramp
transitions. A programmable ALC and Noise Gate mon-
itor the input signals and adjust the volume levels
appropriately.
The DAC output path includes a digital signal process-
ing engine. Tone Control provides bass and treble
adjustment of four selectable corner frequencies. The
Mixer allows independent volume control for both the
ADC mix and the PCM mix, as well as a master digital
volume control for the analog output. All volume level
changes may be configured to occur on soft ramp and
zero-cross transitions. The DAC also includes de-em-
phasis, limiting functions and a beep generator
delivering tones selectable across a range of two full
octaves.
The stereo headphone amplifier is powered from a sep-
arate positive supply and the integrated charge pump
provides a negative supply. This allows a ground-cen-
tered analog output with a wide signal swing and
eliminates external DC-blocking capacitors.
In addition to its many features, the CS42L51 operates
from a low-voltage analog and digital core, making this
codec ideal for portable systems that require extremely
low power consumption in a minimal amount of space.
The CS42L51 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85° C). The CDB42L51 Customer
Demonstration board is also available for device evalu-
ation and implementation suggestions. Please see
“Ordering Information” on page 83 for complete details.
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CS42L51
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11
SPECIFIED OPERATING CONDITIONS ............................................................................................. 11
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 12
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 13
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 15
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 16
LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 17
HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 18
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 19
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 19
SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 21
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 22
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 23
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 23
POWER CONSUMPTION .................................................................................................................... 24
4. APPLICATIONS ................................................................................................................................... 25
4.1 Overview ......................................................................................................................................... 25
4.1.1 Architecture ........................................................................................................................... 25
4.1.2 Line & MIC Inputs .................................................................................................................. 25
4.1.3 Line & Headphone Outputs ................................................................................................... 25
4.1.4 Signal Processing Engine ..................................................................................................... 25
4.1.5 Beep Generator ..................................................................................................................... 25
4.1.6 Device Control (Hardware or Software Mode) ...................................................................... 25
4.1.7 Power Management .............................................................................................................. 25
4.2 Hardware Mode .............................................................................................................................. 26
4.3 Analog Inputs ................................................................................................................................. 27
4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 27
4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 28
4.3.3 Digital Routing ....................................................................................................................... 28
4.3.4 Differential Inputs .................................................................................................................. 28
4.3.5 Analog Input Multiplexer ........................................................................................................ 30
4.3.6 MIC & PGA Gain ................................................................................................................... 30
4.3.7 Automatic Level Control (ALC) .............................................................................................. 31
4.3.8 Noise Gate ............................................................................................................................ 32
4.4 Analog Outputs ............................................................................................................................... 33
4.4.1 De-Emphasis Filter ................................................................................................................ 33
4.4.2 Volume Controls .................................................................................................................... 34
4.4.3 Mono Channel Mixer ............................................................................................................. 34
4.4.4 Beep Generator ..................................................................................................................... 34
4.4.5 Tone Control .......................................................................................................................... 35
4.4.6 Limiter .................................................................................................................................... 35
4.4.7 Line-Level Outputs and Filtering ........................................................................................... 36
4.4.8 On-Chip Charge Pump .......................................................................................................... 37
4.5 Serial Port Clocking ........................................................................................................................ 37
4.5.1 Slave ..................................................................................................................................... 38
4.5.2 Master ................................................................................................................................... 38
4.5.3 High-Impedance Digital Output ............................................................................................. 39
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CS42L51
4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 39
4.6 Digital Interface Formats ................................................................................................................ 39
4.7 Initialization ..................................................................................................................................... 40
4.8 Recommended Power-Up Sequence ............................................................................................. 40
4.9 Recommended Power-Down Sequence ........................................................................................ 41
4.10 Software Mode ............................................................................................................................. 42
4.10.1 SPI Control .......................................................................................................................... 43
4.10.2 I²C Control ........................................................................................................................... 43
4.10.3 Memory Address Pointer (MAP) .......................................................................................... 44
5. REGISTER QUICK REFERENCE ........................................................................................................ 45
6. REGISTER DESCRIPTION .................................................................................................................. 48
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 48
6.2 Power Control 1 (Address 02h) ...................................................................................................... 48
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 49
6.4 Interface Control (Address 04h) ..................................................................................................... 51
6.5 MIC Control (Address 05h) ............................................................................................................. 52
6.6 ADC Control (Address 06h) ............................................................................................................ 53
6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 55
6.8 DAC Output Control (Address 08h) ................................................................................................ 56
6.9 DAC Control (Address 09h) ............................................................................................................ 57
6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ............... 58
6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 59
6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 60
6.13 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 61
6.14 Beep Frequency & Timing Configuration (Address 12h) .............................................................. 61
6.15 Beep Off Time & Volume (Address 13h) ...................................................................................... 62
6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 63
6.17 Tone Control (Address 15h) ......................................................................................................... 64
6.18 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 65
6.19 PCM Channel Mixer (Address 18h) .............................................................................................. 65
6.20 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 66
6.21 Limiter Release Rate Register (Address 1Ah) .............................................................................. 67
6.22 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 68
6.23 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 68
6.24 ALC Release Rate (Address 1Dh) ................................................................................................ 69
6.25 ALC Threshold (Address 1Eh) ...................................................................................................... 69
6.26 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 70
6.27 Status (Address 20h) (Read Only) ............................................................................................... 71
6.28 Charge Pump Frequency (Address 21h) ...................................................................................... 72
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 73
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 73
7.2 Headphone Amplifier Efficiency ...................................................................................................... 75
7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 76
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 77
8.1 Auto Detect Enabled ....................................................................................................................... 77
8.2 Auto Detect Disabled ...................................................................................................................... 78
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 79
9.1 Power Supply, Grounding ............................................................................................................... 79
9.2 QFN Thermal Pad .......................................................................................................................... 79
10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 80
11. PARAMETER DEFINITIONS .............................................................................................................. 81
12. PACKAGE DIMENSIONS ............................................................................................................. 82
4 DS679F2




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