CHD408LVS Datasheet PDF - MIRA

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CHD408LVS
MIRA

Part Number CHD408LVS
Description 4M-Bit Low Power Asynchronous SRAM
Page 11 Pages


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CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
DESCRIPTION
The CHD408L is a family of low voltage, low
power 4Mbit static RAMs organized as
512K-words by 8-bit, designed with Cascade’s
patent pending SuperT-SRAM™ technology,
fabricated with low-power 0.18µm process
technology.
The CHD408LVS is designed specifically for
low-power applications such as mobile cellular
phones, personal digital assistants and other
battery-operated products.
CHD408LVS -55,70 is packaged in sTSOP-I
packages, with normal and reverse lead-bending.
sTSOP-I packages are available in dimensions of
8x12mm and 8x20mm.
FEATURES
Low power
- Low active and standby power for hand-held applications.
- Single power supply.
High Performance
- 55ns or 70ns access time
Compatibility
- 100% compatible with JEDEC asynchronous SRAM.
- No clocks, no refresh.
- No timing restrictions.
- No special power-up sequence requirement.
- Direct TTL compatibility for all inputs and outputs.
Technology
- Designed with Cascade’s patent pending
SuperT-SRAM™ technology.
- Fabricated with low-power 0.18µm process
technology.
Extended temperature range –40 ~ 85°C .
PART NAME TABLE & KEY SPEC SUMMARY
Power Supply
Part Name
2.7V ~ 3.6V
CHD408LVx-70
Max. Access
Time @ 2.7V
70ns
Standby Icc
Max @ 3.0V
85°C
35 µA
Active Icc
3.0V 10MHz
8mA
3.0V ~ 3.6V
CHD408LVx-55
55ns
35 µA
8mA
PART SELECTION TABLE
w Part Name
Package
Lead Bending
ww CHD408LVS-55,70
.D CHD408LVS-55,70-R
atCHD408LVW-55,70
aShCHD408LVW-55,70-R
8x12mm
STSOP-I
8x12m m
STSOP-I
8x20mm
STSOP-I
8x20mm
S TSOP-I
Normal
Reverse
Normal
Reverse
eet4U. Deutron Electronics Corporation
com8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
1



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PIN CONFIGURATION
A11
A9
A8
A13
W
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(TOP VIEW)
CHD408LV
32 Pin sTSOP(I)
32 OE
31 A10
30 S
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
A4
A5
A6
A7
A12
A14
A16
A18
VCC
A15
A17
W
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(TOP VIEW)
CHD408LV-R
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S
31 A10
32 OE
Reverse 32 Pin sTSOP(I)
Pin
A0~A18
DQ1 ~ DQ8
S
W
OE
VCC
GND
Function
Address input
Data input / output
Chip select input
Write control input
Output enable input
Pow er supply
Ground supply
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
2



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FUNCTIONAL DESCRIPTION
CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
CHD408LVS -55/70 (-R) is organized as 512K-words by 8-bit. These devices operate on a single power
supply, and are directly TTL compatible to both input and output. The design uses fully asynchronous static
circuits, requiring no clocks, no refresh, and no special power-up sequence.
The operation modes are determined by a combination of the device control inputs S , W and OE . Each
mode is summarized in the function table.
A write operation is executed whenever the low level W overlaps with the low level S . The address
(A0~A18) must be set up before the write cycle and must be stable during entire cycle.
A read operation is executed by setting W at a high level and OE at a low level while S is in an active
state.
When setting S at a high level, the chip is in a non-select mode. In this mode, the output stage is in a
high-impedance state, allowing OR -tie with other chips.
When OE is at a high level, the output stage is in a high-impedance state.
FUNCTION TABLE
S OE W
H X(1)
X
LH
H
LL H
LXL
DQ1 -8
Z(2)
Z
Data out
Data in
Mode
Deselected
Output
disabled
read
write
Power
Standby
Active
Active
Active
Notes :
(1) X means don’t-care, but must drive to either high or low.
(2) Z means high impedance state.
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
3



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ABSOLUTE MAXIMUM RATINGS
CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
VCC
VI
VO
PD
Tsolder
Tstor
Toper
Parameter
Power Supply
Voltage
Input Voltage
Output Voltage
Power Dissipation
Soldering
Temperature
Storage
Temperature
Operating
Temperature
Value
-0.4 to 4.6
-0.4* to VCC+0.5
(max 4.6)
0 to VCC
0.5
260
-65 to 150
-40 to 85
Unit
V
V
V
W
°C
°C
°C
Notes
* -3V for AC pulse (<30ns)
DC ELECTRICAL CHARACTERISTIC S (T = -40 to 85°C)
VCC
VIH
VIL
VOH
VOL
II
IO
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
High-Level Output Voltage
Low-level Output Voltage
Input Leakage Current
Output Leakage Current
* -3V for AC pulse (<= 30ns)
Conditions
IOH=-1mA
IOL=2mA
VI=0~VCC
Output disabled.
VI/O=0~VCC
Min
2.7/3.0
2.2
-0.4*
VCC-0.4
-
-
-
Typ Max Units
- 3.6 V
- Vcc+0.4 V
- 0.6 V
- -V
- 0.4 V
- ±1 µA
- ±1 µA
POWER CONSUMPTION CHARACTERISTICS
ICC1 10MHz
ICC1 1MHz
ICC2 10MHz
ICC2 1MHz
ISB1
ISB2
Parameter
CMOS-Level Active
Current at f=10MHz
CMOS-Level Active
Currentat f=1MHz
TTL-Level Active
Current at f=10MHz
TTL-Level Active
Currentat f=1MHz
Standby Current
( CMOS Level )
Standby Current
( TTL Level )
Conditions
Output open.
All inputs = 0.2V or
VCC-0.2V
Output open.
All inputs = 0.2V or
VCC-0.2V
Output open.
All inputs = VIL or VIH
Output open.
All inputs = VIL or VIH
S = VCC-0.2V
All other inputs = 0.2 or
VCC-0.2V
S = VIH
All other inputs = VIH or
VIL
Typ Max
(3.0V)
Max
(3.6V)
Units
-8
10 m A
-2
-9
-3
- 35
3 mA
11 m A
4 mA
60 µA
- 0.3
- mA
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
4



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