CH7510 Datasheet PDF - Chrontel


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CH7510
Chrontel

Part Number CH7510
Description DisplayPort Receiver
Page 7 Pages

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Chrontel
CH7510
Brief Datasheet
CH7510 DisplayPort Receiver with Integrated mini-LVDS Timing
Controller (TCON)
FEATURES
GENERAL DESCRIPTION
Fully compliant with DisplayPort Specification version Chrontel’s CH7510 is a low-cost, low-power semi-
1.1a and Embedded DisplayPort (eDP) Specification conductor device that integrates a mini-LVDS timing
version 1.2.
controller (TCON). This device receives high-speed
Support 2 Main Link Lanes at 1.62Gb/s or 2.7Gb/s link serialized video data and uses the Block Diagram, fully
rate programmable TCON to drive the LCD panel modules
Support LCD panel with resolution up to 1920x1200 through integrated mini-LVDS interface, which is
@60Hz or 1366x768@120Hz.
operating in low-voltage and low EMI emission.
Support 6 pairs and 8 pairs mini-LVDS output for both
6-bit and 8-bit LCD panel interface, with the maximum The CH7510 is designed to comply with DisplayPort
clock up to 300MHz
Specification 1.1a and Embedded DisplayPort
Flexible TCON output control, and flexible mini-LVDS Specification version 1.2. It supports two Main Link lanes
output mapping
that are capable of receiving data rate running at 1.62Gb/s
Support single clock mode: R/L mini-LVDS data output or 2.7Gb/s. The device can accept input data in 18-bit
with one common mini-LVDS clock.
6:6:6 or 24-bit 8:8:8 RGB digital formats.
Support HDCP Amendment for Displayport Rev.1.1
Support Gamma correction control
The high performance CH7510’s TCON consists of
Support dithering and 6-bit + FRC
Support Enhanced Framing Mode
programmable logic blocks for processing input video
Support eDP Authentication: Alternative Scramble Seed data, configurable timing control signals and video data to
Reset and Alternative Framing
interface LCD Gate Drivers and Source Drivers. During
2 external clock configuration: 27MHz crystal, 27MHz system power up, setting the power on/off sequence for a
reference clock
particular LCD panel can be achieved through CH7510’s
Support 2-level and 3-level Gate Drivers (output STV1 TCON configuration registers. This timing control
and STV2 at the same time), 8 programmable GPOs for information is stored in the BOOT ROM along with the
driving Source or Gate drivers in TFT LCD panel
Programmable LCD panel power sequence
Support internal test pattern
EDID information that will be used during the Link
Training through AUX Channel.
Blank panel during invalid input
Support OSD display when GPIO
pins
control
Back-
The
CH7510
has
a
luminance
control
function to
adjust
light Luminance
LCD backlight. The brightness control command sent
Supports PWM. Backlight luminance level control through AUX Channel can be dynamically translated by
through AUX channel, and GPIO pin Support Dynamic CH7510 and converted into LCD backlight control signal.
Backlight Control (OSD display)
The CH7510 will save the last setting of brightness level
Support analog current interface for light sensor
value in the BOOT ROMand use it upon power up.
Support loading of CH9904 BOOT ROM when power
up Advanced Power Management Unit (PMU) is designed to
Support updating BOOT ROM through I2C Slave or reduce power consumption in normal operation.
AUX CH
Programmable power management. Support Hardware
fully power down control
Spread spectrum control is available for transmitting
mini-LVDS signal
Hot Plug Detection
Achieve bit error rate <10-9 for raw transport data per
lane and symbol error rate <10-12 for control data
Offered in a 68-pin QFN package
209-1000-024 Rev 0.3
2012-7-24
1



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CHRONTEL
CH7510
27M
HPD
HPD
Generator
PLL
DP
Main Link
Main Link Rx
(2 Lane)
Stream
Sinks
AUX
AUX
Controller
HDCP
DPCD
BIST
Bist Generator
Gamma
Correction
& Dithering
& FRC
Mini LVDS
Mux Tx
OSD
GPO
Generator
Mini LVDS
Source Driver
/Gate Driver
/Power Control
GPIO & IIC Controller
Boot ROM/
EDID
PWM IIC Power Light
Backlight
In/Out
Down Sensor Brightness Control
Figure 1: Functional Block Diagram
Power
Down
Crystal or
Reference
clock
PWM
DP
CH7510
6 / 8 bits Mini-LVDS
Source
Driver Control
Gate Driver
Control
First
Pixel
Source Driver
LCD
Backlight
Brightness
Control
Light
Sensor
Boot ROM
/ EDID
/HDCP Key
PWM
Backlight Enable
Power Enable
Backlight Unit
Last
Pixel
DC/DC Converter & LED
Converter & Power module
Figure 2: System Application Diagram
2 209-1000-024 Rev 0.3 2012-7-24



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CHRONTEL
1.0 PIN ASSIGNMENT
1.1 Package Diagram
CH7510
RB
RESERVED
VDDPLL
VDDPLL
XO
XI
DVDD
DGND
REFCK
LLV3P
LLV3N
LLV2P
LLV2N
LLVCLKP
LLVCLKN
LLV1P
LLV1N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CHRONTEL
CH7510
QFN 68
51 SPC1
50 SPD1
49 PWM_IN
48 PWM_OUT
47 GPO[7]
46 GPO[6]
45 DGND
44 AUXP
43 AUXN
42 DVDD
41 PWRDN
40 AGND
39 GPO[4]
38 GPO[3]
37 GPO[2]
36 BIST
35 AGND
Figure 2: CH7510 68-pin QFN pin out
1.2 Pin Description
Table 1: Pin Description
Pin # Type
Symbol
1 In
RB
2
5,6 In
9 In
RESERVED
XO, XI
REFCK
10~17, Out
19,20,
22~31
LLV[3:0]P/N,
LLVCLKP/N,
RLV[3:0]P/N,
RLVCLKP/N,
Description
Reset Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When
this pin is high, reset is controlled through the serial port register.
Reserved Pin
27MHz Crystal Input
Reference Clock Input
This pin is used as clock input pin when injecting 27/14.318MHz clock to
CH7510
mini-LVDS Output
LLV0P/N ~ LLV3P/N: Left channel data
LLVCLKP/N: Left channel clock
RLV0P/N ~ RLV3P/N: Right channel data
RLVCLKP/N: Right channel clock
33,34,36 Out
~39,57
209-1000-024
GPO[5: 0]
Rev 0.3
Refer to register description part for detailed mini-LVDS pin mapping
LCD Source/Gate Driver Control
2012-7-24
3



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CHRONTEL
~39,57
36 In
41 In
BIST
PWRDN
43 In/Out AUXN
44 In/Out AUXP
46 Out
GPO[6]
47 Out
GPO[7]
48 Out
PWM_OUT
49 In
PWM_IN
50 In/Out SPD1
51 Out
SPC1
53 In/Out SPD0
54 In
SPC0
55 In
56 In
58 In
59 Out
61,62 In
BLDN
BLUP
LSENSOR
HPDET
RXP0, RXN0
CH7510
Refer to register description for detailed GPO mapping
BIST Enable for TCON application
Power Down Control
CH7510 enters/exit power down state when receiving active low pulse from
this pin
Aux channel differential negative input/output
Aux channel differential positive input/output
General Purpose Output Pin
LCD panel VCC enable output by default
General Purpose Output Pin
LCD panel backlight enable output by default
PWM output for backlight brightness dimming
PWM Duty Cycle Range: 0~100%(16 steps)
The output Frequency from PWM_OUT0 can be up to 400KHz. Voltage level
is 3.3V.
Bypass PWM input, and while in bypass mode, frequency of PWM_OUT0 can
be up to 1MHz.
Backlight brightness PWM input
PWM_IN has two work modes: Bypass mode and Duty Cycle Multiplication
with AUX CH mode.
In bypass mode, the input frequency to PWM_IN can be up to 1MHz.
In Duty Cycle Multiplication with AUX CH mode, the input frequency to
PWM_IN can be up to 50KHz.
Voltage level is 3.3V.
Serial Port Data Input/Output for Chip BOOT ROM/EDID/HDCP ROM
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 3.3V. Outputs are driven from 0 to 3.3V. This pin
requires an external 4k- 9 kpull up resistor to 3.3V.
Serial Port Clock Output for Chip BOOT ROM/EDID/HDCP ROM
This pin functions as the clock output of the serial port and operates with
output from 0 to 3.3V. This pin requires an external 4k- 9kpull up resistor
to 3.3V.
Serial Port Data Input / Output for CH7510 I2C Slave
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 3.3V. Outputs are driven from 0 to 3.3V. This pin
requires an external 4k- 9 kpull up resistor to 3.3V.
CH7510 serial port device address is 0x21 and transmitted in SPD as
following(MSB transmitted first)
B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 0 0 0 1 R/W
Serial Port Clock Input for CH7510 I2C Slave
This pin functions as the clock input of the serial port and operates with inputs
from 0 to 3.3V. This pin requires an external 4k- 9kpull up resistor to
3.3V.
Decrement Backlight Brightness Input
Increment Backlight Brightness Input
Light Sensor Input
Hot Plug Detect
This output pin indicates whether this device is active or not. It also generates
interrupt pulse as defined by DP standard. Output voltage is 3.3v.
Main link Lane 0 input
One pair of differential data input. It handles clock-embedded high speed
differential data input as DP standard
4 209-1000-024 Rev 0.3 2012-7-24




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